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參數資料
| 型號： | 17512LJC |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Serial Configuration PROMs |
| 中文描述： | 串行配置PROM的 |
| 文件頁數： | 3/10頁 |
| 文件大小： | 72K |
| 代理商： | 17512LJC |
December 10, 1997 (Version 1.1)
5-3
Controlling Serial PROMs
Most connections between the FPGA device and the Serial
PROM are simple and self-explanatory.
The DATA output(s) of the of the Serial PROM(s) drives
the DIN input of the lead FPGA device.
The master FPGA CCLK output drives the CLK input(s)
of the Serial PROM(s).
The CEO output of a Serial PROM drives the CE input
of the next Serial PROM in a daisy chain (if any).
The RESET/OE input of all Serial PROMs is best driven
by the INIT output of the XC3000 or XC4000 lead
FPGA device. This connection assures that the Serial
PROM address counter is reset before the start of any
(re)configuration, even when a reconfiguration is
initiated by a V
CC
glitch. Other methods – such as
driving RESET/OE from LDC or system reset – assume
that the Serial PROM internal power-on-reset is always
in step with the FPGA’s internal power-on-reset, which
may not be a safe assumption.
The CE input of the lead (or only) Serial PROM is driven
by the DONE/PRGM or DONE output of the lead FPGA
device, provided that DONE/PRGM is not permanently
grounded. Otherwise, LDC can be used to drive CE, but
must then be unconditionally High during user
operation. CE can also be permanently tied Low, but
this keeps the DATA output active and causes an
unnecessary supply current of 10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Logic Cell Array and their
associated interconnections are established by a configu-
ration program. The program is loaded either automatically
upon power up, or on command, depending on the state of
the three FPGA mode pins. In Master Mode, the FPGA
automatically loads the configuration program from an
external memory. The Serial Configuration PROM has
been designed for compatibility with the Master Serial
Mode.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial Mode whenever all three of the FPGA mode-
select pins are Low (M0=0, M1=0, M2=0). Data is read from
the Serial Configuration PROM sequentially on a single
data line. Synchronization is provided by the rising edge of
the temporary signal CCLK, which is generated during con-
figuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line and two control lines are
required to configure an FPGA. Data from the Serial Con-
figuration PROM is read sequentially, accessed via the
internal address and bit counters which are incremented on
every valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
FPGA is used only for configuration, it must still be held at
a defined level during normal operation. The XC3000 and
XC4000 families take care of this automatically with an on-
chip default pull-up resistor.
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are
stored in a Serial Configuration PROM, the OE pin should
be tied Low. Upon power-up, the internal address counters
are reset and configuration begins with the first program
stored in memory. Since the OE pin is held Low, the
address counters are left unchanged after configuration is
complete. Therefore, to reprogram the FPGA with another
program, the D/P line is pulled Low and configuration
begins at the last value of the address counters.
This method fails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
Serial PROM does not reset its address counter, since it
never saw a High level on its OE input. The new configura-
tion, therefore, reads the remaining data in the PROM and
interprets it as preamble, length count etc. Since the FPGA
is the master, it issues the necessary number of CCLK
pulses, up to 16 million (24) and D/P goes High. However,
the FPGA configuration will be completely wrong, with
potential contentions inside the FPGA and on its output
pins. This method must, therefore, never be used when
there is any chance of external reset during configuration.
Cascading Serial Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded SCPs provide additional memory. After the last bit
from the first SCP is read, the next clock signal to the SCP
asserts its CEO output Low and disables its DATA line. The
second SCP recognizes the Low level on its CE input and
enables its DATA output. See
Figure 2
.
After configuration is complete, the address counters of all
cascaded SCPs are reset if the FPGA RESET pin goes
Low, assuming the SCP reset polarity option has been
inverted.
To reprogram the FPGA with another program, the D/P line
goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of DIN.
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