- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄22007 > A54SX32A-FGG256 (Microsemi SoC)IC FPGA 249I/O 256FBGA PDF資料下載
參數(shù)資料
| 型號： | A54SX32A-FGG256 |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 20/108頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 249I/O 256FBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | SX-A |
| LAB/CLB數(shù)： | 2880 |
| 輸入/輸出數(shù)： | 203 |
| 門數(shù)： | 48000 |
| 電源電壓： | 2.25 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FPBGA（17x17） |
| 其它名稱： | 1100-1070 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁
SX-A Family FPGAs
v5.3
1-15
Pin Description
CLKA/B, I/O
Clock A and B
These pins are clock inputs for clock distribution
networks. Input levels are compatible with standard TTL,
LVTTL, LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. The
clock input is buffered prior to clocking the R-cells. When
not used, this pin must be tied Low or High (NOT left
floating) on the board to avoid unwanted power
consumption.
For A54SX72A, these pins can also be configured as user
I/Os. When employed as user I/Os, these pins offer built-
in programmable pull-up or pull-down resistors active
during power-up only. When not used, these pins must
be tied Low or High (NOT left floating).
QCLKA/B/C/D, I/O
Quadrant Clock A, B, C, and D
These four pins are the quadrant clock inputs and are
only
used
for
A54SX72A
with
A,
B,
C,
and
D
corresponding to bottom-left, bottom-right, top-left,
and top-right quadrants, respectively. They are clock
inputs for clock distribution networks. Input levels are
compatible with standard TTL, LVTTL, LVCMOS2, 3.3 V
PCI, or 5 V PCI specifications. Each of these clock inputs
can drive up to a quarter of the chip, or they can be
grouped together to drive multiple quadrants. The clock
input is buffered prior to clocking the R-cells. When not
used, these pins must be tied Low or High on the board
(NOT left floating).
These pins can also be configured as user I/Os. When
employed
as
user
I/Os,
these
pins
offer
built-in
programmable pull-up or pull-down resistors active
during power-up only.
GND
Ground
Low supply voltage.
HCLK
Dedicated (Hardwired)
Array Clock
This pin is the clock input for sequential modules. Input
levels
are
compatible
with
standard
TTL,
LVTTL,
LVCMOS2, 3.3 V PCI, or 5 V PCI specifications. This input is
directly wired to each R-cell and offers clock speeds
independent of the number of R-cells being driven.
When not used, HCLK must be tied Low or High on the
board (NOT left floating). When used, this pin should be
held Low or High during power-up to avoid unwanted
static power consumption.
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with standard
TTL, LVTTL, LVCMOS2, 3.3 V PCI or 5 V PCI specifications.
Unused I/O pins are automatically tristated by the
Designer software.
NC
No Connection
This pin is not connected to circuitry within the device
and can be driven to any voltage or be left floating with
no effect on the operation of the device.
PRA/B, I/O
Probe A/B
The Probe pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the other
probe pin to allow real-time diagnostic output of any
signal path within the device. The Probe pin can be used
as a user-defined I/O when verification has been
completed.
The
pin’s
probe
capabilities
can
be
permanently disabled to protect programmed design
confidentiality.
TCK, I/O
Test Clock
Test clock input for diagnostic probe and device
programming. In Flexible mode, TCK becomes active
when the TMS pin is set Low (refer to Table 1-6 on
page 1-9). This pin functions as an I/O when the
boundary scan state machine reaches the "logic reset"
state.
TDI, I/O
Test Data Input
Serial input for boundary scan testing and diagnostic
probe. In Flexible mode, TDI is active when the TMS pin is
set Low (refer to Table 1-6 on page 1-9). This pin
functions as an I/O when the boundary scan state
machine reaches the “l(fā)ogic reset” state.
TDO, I/O
Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set Low (refer to
Table 1-6 on page 1-9). This pin functions as an I/O when
the boundary scan state machine reaches the "logic
reset" state. When Silicon Explorer II is being used, TDO
will act as an output when the checksum command is
run. It will return to user /IO when checksum is complete.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible
mode when the TMS pin is set Low, the TCK, TDI, and
TDO pins are boundary scan pins (refer to Table 1-6 on
page 1-9). Once the boundary scan pins are in test mode,
they will remain in that mode until the internal
boundary scan state machine reaches the logic reset
state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The logic
reset state is reached five TCK cycles after the TMS pin is
set High. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications.
TRST, I/O
Boundary Scan Reset Pin
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active low input to asynchronously
initialize or reset the boundary scan circuit. The TRST pin
is equipped with an internal pull-up resistor. This pin
functions as an I/O when the Reserve JTAG Reset Pin is
not selected in Designer.
VCCI
Supply Voltage
Supply voltage for I/Os. See Table 2-2 on page 2-1. All
VCCI power pins in the device should be connected.
VCCA
Supply Voltage
Supply voltage for array. See Table 2-2 on page 2-1. All
VCCA power pins in the device should be connected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EEM15DTBT | CONN EDGECARD 30POS R/A .156 SLD |
| ESM44DRYI | CONN EDGECARD 88POS DIP .156 SLD |
| GCM06DCTD | CONN EDGECARD 12POS DIP .156 SLD |
| EEM15DTAT | CONN EDGECARD 30POS R/A .156 SLD |
| EMM44DRES | CONN EDGECARD 88POS .156 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX32A-FGG256A | 功能描述:IC FPGA SX 48K GATES 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A54SX32A-FGG256I | 功能描述:IC FPGA SX 48K GATES 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A54SX32A-FGG256M | 制造商:Microsemi Corporation 功能描述:FPGA SX-A Family 32K Gates 1800 Cells 238MHz 0.25um Technology 2.5V 256-Pin FBGA 制造商:Microsemi Corporation 功能描述:FPGA SX-A 32K GATES 1800 CELLS 238MHZ 0.25UM/0.22UM 2.5V 256 - Trays |
| A54SX32A-FGG484 | 功能描述:IC FPGA SX 48K GATES 484-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A54SX32A-FGG484I | 功能描述:IC FPGA SX 48K GATES 484-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。