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參數資料
| 型號： | AD7665ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 570 kSPS CMOS ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | LOW PROFILE, MS-026BBC, QFP-48 |
| 文件頁數： | 3/24頁 |
| 文件大小： | 348K |
| 代理商： | AD7665ASTRL |
REV. 0
–3–
AD7665
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES (Continued)
Power Dissipation
5, 6
444 kSPS Throughput
7
100 SPS Throughput
7
570 kSPS Throughput
4
64
15
93
74
mW
μ
W
mW
μ
W
107
7
In Power-Down Mode
8
TEMPERATURE RANGE
9
Specified Performance
T
MIN
to T
MAX
–40
+85
°
C
NOTES
1
LSB means Least Significant Bit. With the
±
5 V input range, one LSB is 152.588
μ
V.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.
4
In warp mode.
5
Tested in parallel reading mode.
6
Tested with the 0 V to 5 V range and V
IN
– V
INGND
= 0 V. See Power Dissipation section.
7
In impulse mode.
8
With OVDD below DVDD + 0.3 V and all digital inputs forced to OVDD or OGND respectively.
9
Contact factory for extended temperature range.
Specifications subject to change without notice.
Table I. Analog Input Configuration
Input Voltage
Range
±
4 REF
±
2 REF
±
REF
0 V to 4 REF
0 V to 2 REF
0 V to REF
Input
Impedance
1
5.85 k
3.41 k
2.56 k
3.41 k
2.56 k
Note 2
IND (4R)
INC (4R)
INB (2R)
INA (R)
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
INGND
V
IN
V
IN
V
IN
V
IN
V
IN
INGND
INGND
V
IN
INGND
V
IN
V
IN
REF
REF
REF
INGND
INGND
V
IN
NOTES
1
Typical analog input impedance.
2
For this range the input is high impedance.
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12
Convert Pulsewidth
Time Between Conversions
(Warp Mode/Normal Mode/Impulse Mode)
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in Master Serial Read after
Convert Mode (Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
RESET Pulsewidth
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST
LOW to DATA Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
Refer to Figures 17 and 18 (Master Serial Interface Modes)
2
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay (Read During Convert)
(Warp Mode/Normal Mode/Impulse Mode)
t
1
t
2
5
1.75/2/2.25
ns
μ
s
Note 1
t
3
t
4
30
0.75/1/1.25
ns
μ
s
t
5
t
6
t
7
t
8
t
9
2
ns
ns
μ
s
μ
s
ns
10
0.75/1/1.25
1
10
t
10
0.75/1/1.25
μ
s
t
11
t
12
t
13
20
ns
ns
ns
40
15
5
t
14
t
15
t
16
t
17
10
10
10
ns
ns
ns
ns
25/275/525
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
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