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參數(shù)資料
| 型號： | AD7703CR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| 中文描述： | 1-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | MS-013AC, SOIC-20 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 251K |
| 代理商： | AD7703CR |
AD7703
REV. D
–13–
T herefore, the two analog supplies should be individually
decoupled to AGND using 100 nF ceramic capacitors to
provide power supply noise rejection at these frequencies. T he
two digital supplies should similarly be decoupled to DGND.
T he positive digital supply (DV
DD
) must never exceed the
positive analog supply (AV
DD
) by more than 0.3 V. Power
supply sequencing is therefore important. If separate analog and
digital supplies are used, care must be taken to ensure that the
analog supply is powered up first.
It is also important that power is applied to the AD7703 before
signals at V
REF
, A
IN
or the logic input pins in order to avoid any
possibility of latch-up. If separate supplies are used for the
AD7703 and the system digital circuitry, then the AD7703
should be powered up first.
A typical scheme for powering the AD7703 from a single set of
±
5 V rails is shown Figure 7. In this circuit AV
DD
and DV
DD
are
brought along separate tracks from the same +5 V supply.
T hus, there is no possibility of the digital supply coming up
before the analog supply.
SLE E P MODE
T he low power standby mode is initiated by taking the
SLEEP
input low, which shuts down all analog and digital circuits and
reduces power consumption to 10
μ
W. When coming out of
SLEEP mode it is sometimes possible (when using a crystal to
generate CLK IN, for example) to lose the calibration coeffi-
cients. T herefore, it is advisable as a safeguard to always do a
calibration cycle after coming out of SLEEP mode.
DIGIT AL INT E RFACE
T he AD7703’s serial communications port allows easy
interfacing to industry standard microprocessors. T wo different
modes of operation are available, optimized for different types
of interface.
VOLT AGE RE FE RE NCE CONNE CT IONS
T he voltage applied to the V
REF
pin defines the analog input
range. T he specified reference voltage is 2.5 V, but the AD7703
will operate with reference voltages from 1 V to 3 V with little
degradation in performance.
T he reference input presents exactly the same dynamic load as
the analog input, but in the case of the reference input, source
resistance and long settling time introduce gain errors rather
than offset errors. Fortunately, most precision references have
sufficiently low output impedance and wide enough bandwidth
to settle to the required accuracy within 62 clock cycles.
T he digital filter of the AD7703 removes noise from the refer-
ence input, just as it does with noise at the analog input, and
the same limitations apply regarding lack of noise rejection at
integer multiples of the sampling frequency. Note that the refer-
ence should be chosen to minimize noise below 10 Hz. T he
AD7703 typically exhibits 1.6 LSB rms noise in its measure-
ments. T his specification assumes a clean reference. Many
monolithic bandgap references are available which can supply
the 2.5 V needed for the AD7703. However, some of these are
not specified for noise especially in the 0.1 Hz to 10 Hz band-
width. If the reference noise in this bandwidth is excessive, it
can degrade the performance of the AD7703. Recommended
references are the AD580 and the LT 1019. Both of these 2.5 V
references typically have less than 10
m
V p-p noise in the 0.1 Hz
to 10 Hz band.
POWE R SUPPLIE S AND GROUNDING
AGND is the ground reference voltage for the AD7703, and is
completely independent of DGND. Any noise riding on the
AGND input with respect to the system analog ground will
cause conversion errors. AGND should therefore be used as the
system ground and also as the ground for the analog input and
the reference voltage.
T he analog and digital power supplies to the AD7703 are
independent and separately pinned out, to minimize coupling
between analog and digital sections of the device. T he digital
filter will provide rejection of broadband noise on the power
supplies, except at integer multiples of the sampling frequency.
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| AD7703SQ | LC2MOS 20-Bit A/D Converter |
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| AD7705BN | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| AD7705BR | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD7703CR-REEL | 功能描述:IC ADC 20BIT LC2MOS MONO 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7703CRZ | 功能描述:IC ADC 20BIT LC2MOS MONO 20SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7703SQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS 20-Bit A/D Converter |
| AD7705 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
| AD7705_06 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs |
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