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參數(shù)資料
| 型號(hào)： | AD7705BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| 中文描述： | 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | 0.300 INCH, MS-013AA, SOIC-16 |
| 文件頁(yè)數(shù)： | 10/32頁(yè) |
| 文件大小： | 264K |
| 代理商： | AD7705BR |
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AD7705/AD7706
–10–
REV. A
ON-CHIP REGISTERS
The AD7705/AD7706 contains eight on-chip registers which can be accessed via the serial port of the part. The first of these is a
Communications Register that controls the channel selection, decides whether the next operation is a read or write operation and
also decides which register the next read or write operation accesses. All communications to the part must start with a write opera-
tion to the Communications Register. After power-on or
RESET
, the device expects a write to its Communications Register. The
data written to this register determines whether the next operation to the part is a read or a write operation and also determines to
which register this read or write operation occurs. Therefore, write access to any of the other registers on the part starts with a write
operation to the Communications Register followed by a write to the selected register. A read operation from any other register on
the part (including the Communications Register itself and the output data register) starts with a write operation to the Communica-
tions Register followed by a read operation from the selected register. The Communications Register also controls the standby mode
and channel selection and the
DRDY
status is also available by reading from the Communications Register. The second register is a
Setup Register that determines calibration mode, gain setting, bipolar/unipolar operation and buffered mode. The third register is
labelled the Clock Register and contains the filter selection bits and clock control bits. The fourth register is the Data Register from
which the output data from the part is accessed. The final registers are the calibration registers which store channel calibration data.
The registers are discussed in more detail in the following sections.
Communications Register (RS2, RS1, RS0 = 0, 0, 0)
The Communications Register is an 8-bit register from which data can either be read or to which data can be written. All communi-
cations to the part must start with a write operation to the Communications Register. The data written to the Communications Reg-
ister determines whether the next operation is a read or write operation and to which register this operation takes place. Once the
subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to
the Communications Register. This is the default state of the interface, and on power-up or after a
RESET
, the AD7705/AD7706 is
in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost,
if a write operation of sufficient duration (containing at least 32 serial clock cycles) takes place with DIN high, the AD7705 returns
to this default state. Table V outlines the bit designations for the Communications Register.
Table V.Communications Register
0/
DRDY
(0)
RS2 (0)
RS1 (0)
RS0 (0)
R/
W
(0)
STBY (0)
CH1 (0)
CH0 (0)
0/
DRDY
For a write operation, a “0” must be written to this bit so that the write operation to the Communications Register
actually takes place. If a “1” is written to this bit, the part will not clock on to subsequent bits in the register. It
will stay at this bit location until a “0” is written to this bit. Once a “0” is written to this bit, the next seven bits
will be loaded to the Communications Register. For a read operation, this bit provides the status of the
DRDY
flag
from the part. The status of this bit is the same as the
DRDY
output pin.
Register Selection Bits. These three bits select to which one of eight on-chip registers the next read or write opera-
tion takes place, as shown in Table VI, along with the register size. When the read or write operation to the se-
lected register is complete, the part returns to where it is waiting for a write operation to the Communications
Register. It does not remain in a state where it will continue to access the register.
RS2–RS0
TEMPERATURE –
8
C
–40
S
m
A
0
4
8
16
20
12
–30 –20 –10
0
10
20
30
40
50
60
70
80
V
DD
= 5V
V
DD
= 3V
MCLK IN = 0V OR V
DD
Figure 9. Standby Current vs. Temperature
CH1 5.00V
CH2 2.00V
2
2
1
TEK STOP: SINGLE SEQ 50.0kS/s
V
DD
OSCILLATOR = 4.9152 MHz
OSCILLATOR = 2.4576 MHz
5ms/DIV
Figure 8. Typical Crystal Oscillator Power-Up Time
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7705BRU | 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
| AD7706 | 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
| AD7706BN | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| AD7706BR | 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
| AD7706BRU | 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
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參數(shù)描述 |
|---|---|
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