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參數(shù)資料
| 型號： | AD7818ARZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 279K |
| 描述： | IC ADC 10BIT W/TEMP SENSOR 8SOIC |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 98 |
| 功能： | 溫度監(jiān)控系統(tǒng)（傳感器） |
| 傳感器類型： | 內(nèi)部 |
| 感應(yīng)溫度： | -55°C ~ 125°C |
| 精確度： | ±2°C |
| 拓撲： | ADC，多路復用器，寄存器庫 |
| 輸出類型： | MICROWIRE?，QSPI?，SPI? |
| 輸出警報： | 是 |
| 輸出風扇： | 是 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 管件 |
REV. C
AD7816/AD7817/AD7818
5
TIMING CHARACTERISTICS
1, 2
Parameter
A, B Versions
Unit
Test Conditions/Comments
t
POWER-UP
2
祍 max
Power-Up Time from Rising Edge of CONVST
t
1a
9
祍 max
Conversion Time Channels 1 to 4
t
1b
27
祍 max
Conversion Time Temperature Sensor
t
2
20
ns min
CONVST Pulse Width
t
3
50
ns max
CONVST Falling Edge to BUSY Rising Edge
t
4
0
ns min
CS Falling Edge to RD/WR Falling Edge Setup Time
t
5
0
ns min
RD/WR Falling Edge to SCLK Falling Edge Setup
t
6
10
ns min
D
IN
Setup Time before SCLK Rising Edge
t
7
10
ns min
D
IN
Hold Time after SCLK Rising Edge
t
8
40
ns min
SCLK Low Pulse Width
t
9
40
ns min
SCLK High Pulse Width
t
10
0
ns min
CS Falling Edge to RD/WR Rising Edge Setup Time
t
11
0
ns min
RD/WR Rising Edge to SCLK Falling Edge Setup Time
t
12
3
20
ns max
D
OUT
Access Time after RD/WR Rising Edge
t
13
3
20
ns max
D
OUT
Access Time after SCLK Falling Edge
t
14a
3, 4
30
ns max
D
OUT
Bus Relinquish Time after Falling Edge of RD/WR
t
14b
3, 4
30
ns max
D
OUT
Bus Relinquish Time after Rising Edge of CS
t
15
150
ns max
BUSY Falling Edge to OTI Falling Edge
t
16
40
ns min
RD/WR Rising Edge to OTI Rising Edge
t
17
400
ns min
SCLK Rising Edge to CONVST Falling Edge (Acquisition Time of T/H)
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to
90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 16, 17, 20 and 21.
3
These figures are measured with the load circuit of Figure 3. They are defined as the time required for D
OUT
to cross 0.8 V or 2.4 V for V
DD
= 5 V 10% and 0.4 V
or 2 V for V
DD
= 3 V 10%, as quoted on the specifications page of this data sheet.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6V
I
OL
200A
200A
I
OL
TO
OUTPUT
PIN
C
L
50pF
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
(V
DD
= 2.7 V to 5.5 V, GND = 0 V, REF
IN
= 2.5 V. All specifications T
MIN
to T
MAX
unless
otherwise noted)
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