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參數資料
| 型號： | AD7871JN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Complete 14-Bit, Sampling ADCs |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數： | 12/16頁 |
| 文件大小： | 344K |
| 代理商： | AD7871JN |
AD7871/AD7872
–12–
REV. D
Serial Interfacing
Both the AD7871 and the AD7872 have an identical serial in-
terface. T he diagrams that follow show the AD7872 interfaces
only, but the AD7871 could just as easily be used in these cir-
cuits. Figures 19, 20 and 21 show the AD7872 connected to
three popular DSPs. In all three interfaces,
CONVST
is used to
start conversion since this does not activate the parallel bus.
T hus, the microprocessor can continue to use its parallel bus re-
gardless of the state of the AD7872. T he interfaces show a timer
driving the
CONVST
input but this could be generated from a
decoded address if required.
AD7872–DSP56000 Serial Interface
Figure 19 shows a serial interface between the AD7872 and the
DSP56000. T he interface arrangement is two-wire with the
AD7872 configured for noncontinuous clock operation CON-
T ROL = 0 V). T he DSP56000 is configured for Normal Mode
Asynchronous Operation with Gated Clock. It is set up for a
16-bit word with SCK as an input and the FSL control bit set to
a 0. In this configuration, the DSP56000 assumes valid data on
the first falling edge of SCK . Since the AD7872 provides valid
data on this first edge, there is no need for a strobe or framing
pulse for the data. SCLK and SDAT A are three-stated when the
AD7872 is not performing a conversion. During conversion,
data is valid on the SDAT A output of the AD7872 and is
clocked into the Receive Data Shift Register of the DSP56000.
When this register has received 16 bits of data, it generates an
internal interrupt on the DSP56000 to read the data from the
register.
Figure 19. AD7872 to DSP56000 Interface
T he DSP56000 and AD7872 can also be configured for con-
tinuous clock operation. In this case a strobe pulse is required
by the DSP56000 to indicate when data is valid. T he
SSTRB
output of the AD7872 is inverted and applied to the SC1 input
of the DSP56000 to provide this strobe pulse. All other condi-
tions and connections are the same as for the gated clock
operation.
AD7872–TMS32020/C25 Serial Interface
Figure 20 shows a serial interface between the AD7872 and the
T MS32020/C25. T he AD7872 is configured for continuous
clock operation. Note, the ADC will not interface correctly to
the T MS32020/C25 if it is configured for a noncontinuous
clock. Data is clocked into the Data Receive Register (DRR) of
the T MS32020/C25 during conversion. As with the previous in-
terfaces, when a 16-bit word is received by the DSP it generates
an internal interrupt to read the data from the DRR.
Figure 20. AD7872 to TMS32020/C25 Interface
AD7872–ADSP-2101/ADSP-2102 Serial Interface
Figure 21 shows a serial interface between the AD7872 and the
ADSP-2101/ADSP-2102 DSP Microcomputer. T he AD7872 is
configured for continuous clock operation. Data is clocked into
the serial port register of the microcomputer during conversion.
As with the previous interfaces, when a 16-bit data word is re-
ceived by the ADSP-2101/ADSP-2102 an internal microproces-
sor interrupt is generated and the data is read from the serial
port register.
Figure 21. AD7872 to ADSP-2101/ADSP-2102 Serial Interface
ST AND-ALONE OPE RAT ION
T he AD7871 can be used in its Mode 2, parallel mode for
stand-alone operation. In this case, conversion is initiated with a
pulse to the
CS
input. T his pulse must be longer than the con-
version time of the ADC. T he
BUSY
output is used to drive the
RD
input. Data is latched from the AD7871 DB0–DB11 out-
puts to an external latch on the rising edge of
BUSY
.
APPLICAT ION HINT S
Good printed circuit board (PCB) layout is as important as the
circuit design itself in achieving high speed A/D performance.
T he AD7871/AD7872 is required to make bit decisions on an
LSB size of 366
μ
V. T hus, the designer has to be conscious of
noise both in the ADC itself and in the preceding analog cir-
cuitry. Switching mode power supplies are not recommended as
the switching spikes will feed through to the comparator causing
noisy code transitions. Other causes of concern are ground loops
and digital feedthrough from microprocessors. T hese are factors
that influence any ADC; a proper PCB layout that minimizes
these effects is essential for best performance.
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