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參數資料
| 型號： | AD8063AR-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital Converter 20-SSOP |
| 中文描述： | OP-AMP, 6000 uV OFFSET-MAX, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數： | 14/16頁 |
| 文件大小： | 314K |
| 代理商： | AD8063AR-REEL7 |
AD8061/AD8062/AD8063
–14–
REV. C
Figure 8 shows a unity gain follower using the series resistor
strategy. The resistor isolates the output from the capacitance
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.
AD8061
V
O
R
SERIES
C
LOAD
V
IN
Figure 8. Series Resistor Isolating Capacitive Load
Voltage feedback amplifiers like those in AD806x family will be
able to drive more capacitive load without excessive peaking
when used in higher-gain configurations. This is because the
increased noise gain reduces the bandwidth of the overall feed-
back loop. Figure 9 plots the capacitance that produces 30%
overshoot versus noise gain for a typical amplifier.
CLOSED-LOOP GAIN
10000
1000
101
5
2
C
–
100
3
4
R
S
= 0
R
S
= 4.7
Figure 9. Capacitive Load vs. Closed-Loop Gain
DISABLE OPERATION
The internal circuit for the AD8063 disable function is shown in
Figure 10. When the
DISABLE
node is pulled below 2 V from
the positive supply, the supply current will decrease from typi-
cally 6.5 mA to under 400
μ
A, and the AD8063 output will
enter a high impedance state. If the
DISABLE
node is not con-
nected, and thus is allowed to float, the AD8063 will stay biased
at full power.
VCC
DISABLE
TO AMPLIFIER
BIAS
VEE
2V
Figure 10. Disable Circuit of the AD8063
TPC 28 shows AD8063 supply current versus
DISABLE
volt-
age. TPC 29 plots the output seen when the AD8063 input is
driven with a 10 MHz sine wave, and the
DISABLE
is toggled
from 0 V to 5 V, illustrating the part’s turn-on and turn-off time.
TPC 27 shows the input/output isolation response with the
AD8063 shut off.
BOARD LAYOUT CONSIDERATIONS
Maintaining the high-speed performance of the AD806x family
requires the use of high-speed board layout techniques and low
parasitic components.
The PCB should have a ground plane covering unused portions
of the component side of the board to provide a low impedance
path. The ground plane should be removed near the package to
reduce parasitic capacitance.
Proper bypassing is critical. A ceramic 0.1
μ
F chip capacitor
should be used to bypass both supplies, and be located within
3 mm of each power pin. An additional 4.7
μ
F to 10
μ
F tanta-
lum electrolytic capacitor should be connected in parallel to
provide charge for fast, large signal changes at the output.
Minimizing parasitic capacitance at the amplifier’s inverting
input pin is very important. The feedback resistor should be
located close to the inverting input pin. The value of the feed-
back resistor may come into play—for instance, 1 k
interacting
with 1 pF of parasitic capacitance creates a pole at 159 MHz.
Stripline design techniques should be used for signal traces
longer than 25 mm. These should be designed with either 50
or 75
characteristic impedance and be properly terminated at
each end.
APPLICATIONS
Single Supply Sync Stripper
When a video signal contains synchronization pulses, it is
sometimes desirable to remove them prior to performing
certain operations. In the case of A-to-D conversion, the sync
pulses will consume some of the dynamic range, so removing
them will increase the converter’s available dynamic range for
the video information.
Figure 11 shows a basic circuit for creating a sync stripper using
the AD8061 powered by a single supply. When the nega-
tive supply is at ground potential, the lowest potential to
which the output can go is ground. This feature is exploited
to create a waveform whose lowest amplitude is the black level
of the video and does not include the sync level.
75
VIDEO OUT
75
R
G
1k
75
R
F
1k
10 F
3V
AD8061
0.1 F
3
2
4
6
7
VIDEO IN
PIN NUMBERS ARE
FOR 8-PIN PACKAGE
Figure 11. Single 3 V Sync Stripper Using AD8061
In this case, the input video signal has its black level at ground,
so it comes out at ground at the input. Since the sync level is below
the black level, it will not show up at the output. However, all
of the active video portion of the waveform will be amplified
by a gain of two and then be normalized to unity gain by the
back-terminated transmission line. Figure 12 is an oscilloscope
plot of the input and output waveforms.
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