- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄22011 > EP1K50QC208-1N (Altera)IC ACEX 1K FPGA 50K 208-PQFP PDF資料下載
參數(shù)資料
| 型號： | EP1K50QC208-1N |
| 廠商： | Altera |
| 文件頁數(shù)： | 16/86頁 |
| 文件大小： | 0K |
| 描述： | IC ACEX 1K FPGA 50K 208-PQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 144 |
| 系列： | ACEX-1K® |
| LAB/CLB數(shù)： | 360 |
| 邏輯元件/單元數(shù)： | 2880 |
| RAM 位總計： | 40960 |
| 輸入/輸出數(shù)： | 147 |
| 門數(shù)： | 199000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 其它名稱： | 544-1843 EP1K50QC208-1N-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
Altera Corporation
23
ACEX 1K Programmable Logic Device Family Data Sheet
D
e
ve
lo
pm
e
n
t
13
To
o
ls
Clearable Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
it supports a synchronous clear instead of the up/down control. The clear
function is substituted for the cascade-in signal in the up/down counter
mode. Two 3-input LUTs are used; one generates the counter data, and the
other generates the fast carry bit. Synchronous loading is provided by a
2-to-1 multiplexer. The output of this multiplexer is AND ed with a
synchronous clear signal.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. However, if multiple OE signals are active, contending signals can be
driven onto the bus. Conversely, if no OE signals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and preset control structure of the LE asynchronously loads signals
into a register. Either LABCTRL1 or LABCTRL2 can control the
asynchronous clear. Alternatively, the register can be set up so that
LABCTRL1
implements an asynchronous load. The data to be loaded is
driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the
register.
During compilation, the compiler automatically selects the best control
signal implementation. Because the clear and preset functions are active-
low, the Compiler automatically assigns a logic high to an unused clear or
preset.
The clear and preset logic is implemented in one of the following six
modes chosen during design entry:
■
Asynchronous clear
■
Asynchronous preset
■
Asynchronous clear and preset
■
Asynchronous load with clear
■
Asynchronous load with preset
■
Asynchronous load without clear or preset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-BNW-CX | CONVERTER MOD DC/DC 5.5V 75W |
| 3-1624113-1 | INDUCTOR 15NH 5% 0805 |
| VI-BNW-CW | CONVERTER MOD DC/DC 5.5V 100W |
| AIMC-0603-15NJ-T | INDUCTOR MULTILAYER 15NH 0603 |
| VI-BNV-CX | CONVERTER MOD DC/DC 5.8V 75W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1K50QC208-1P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QC208-1X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QC208-2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K50QC208-2F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QC208-2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。