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參數資料
| 型號： | EP1K50TC144-1 |
| 廠商： | Altera |
| 文件頁數： | 36/86頁 |
| 文件大小： | 0K |
| 描述： | IC ACEX 1K FPGA 50K 144-TQFP |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 180 |
| 系列： | ACEX-1K® |
| LAB/CLB數： | 360 |
| 邏輯元件/單元數： | 2880 |
| RAM 位總計： | 40960 |
| 輸入/輸出數： | 102 |
| 門數： | 199000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
| 其它名稱： | 544-1072 |
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Altera Corporation
41
ACEX 1K Programmable Logic Device Family Data Sheet
D
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lo
pm
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13
To
o
ls
The VCCINT pins must always be connected to a 2.5-V power supply.
With a 2.5-V VCCINT level, input voltages are compatible with 2.5-V, 3.3-
V, and 5.0-V inputs. The VCCIO pins can be connected to either a 2.5-V or
3.3-V power supply, depending on the output requirements. When the
VCCIO
pins are connected to a 2.5-V power supply, the output levels are
compatible with 2.5-V systems. When the VCCIO pins are connected to a
3.3-V power supply, the output high is at 3.3 V and is therefore compatible
with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels higher
than 3.0 V achieve a faster timing delay of tOD2 instead of tOD1.
Table 13 summarizes ACEX 1K MultiVolt I/O support.
Notes:
(1)
The PCI clamping diode must be disabled on an input which is driven with a
voltage higher than VCCIO.
(2)
When VCCIO = 3.3 V, an ACEX 1K device can drive a 2.5-V device that has 3.3-V
tolerant inputs.
Open-drain output pins on ACEX 1K devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a higher
VIH than LVTTL. When the open-drain pin is active, it will drive low.
When the pin is inactive, the resistor will pull up the trace to 5.0 V, thereby
meeting the CMOS VOH requirement. The open-drain pin will only drive
low or tri-state; it will never drive high. The rise time is dependent on the
value of the pull-up resistor and load impedance. The IOL current
specification should be considered when selecting a pull-up resistor.
Power
Sequencing &
Hot-Socketing
Because ACEX 1K devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. The VCCIO and VCCINT power planes can be powered in any
order.
Signals can be driven into ACEX 1K devices before and during power up
without damaging the device. Additionally, ACEX 1K devices do not
drive out during power up. Once operating conditions are reached,
ACEX 1K devices operate as specified by the user.
Table 13. ACEX 1K MultiVolt I/O Support
VCCIO (V)
Input Signal (V)
Output Signal (V)
2.5
3.3
5.0
2.5
3.3
5.0
2.5
v
v (1)
v
3.3
vv
v (1)
v (2)
vv
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EP1K50TC144-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50TC144-1F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50TC144-1N | 功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 360 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K50TC144-1P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50TC144-1X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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