- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄22003 > EPF10K30RC208-4 (Altera)IC FLEX 10K FPGA 30K 208-RQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | EPF10K30RC208-4 |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 74/128頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FLEX 10K FPGA 30K 208-RQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 產(chǎn)品變化通告： | Package Change 30/Jun/2010 |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 系列： | FLEX-10K® |
| LAB/CLB數(shù)： | 216 |
| 邏輯元件/單元數(shù)： | 1728 |
| RAM 位總計(jì)： | 12288 |
| 輸入/輸出數(shù)： | 147 |
| 門(mén)數(shù)： | 69000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 240-RQFP（32x32） |
| 其它名稱： | 544-2229 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)當(dāng)前第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
Altera Corporation
5
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
FLEX 10K and FLEX 10KA device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), pin-grid array (PGA),
and FineLine BGATM packages.
(2)
This option is supported with a 256-pin FineLine BGA package. By using SameFrame pin migration, all FineLine
BGA packages are pin compatible. For example, a board can be designed to support both 256-pin and 484-pin
FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set.
General
Description
Altera’s FLEX 10K devices are the industry’s first embedded PLDs. Based
on reconfigurable CMOS SRAM elements, the Flexible Logic Element
MatriX (FLEX) architecture incorporates all features necessary to
implement common gate array megafunctions. With up to 250,000 gates,
the FLEX 10K family provides the density, speed, and features to integrate
entire systems, including multiple 32-bit buses, into a single device.
FLEX 10K devices are reconfigurable, which allows 100
% testing prior to
shipment. As a result, the designer is not required to generate test vectors
for fault coverage purposes. Additionally, the designer does not need to
manage inventories of different ASIC designs; FLEX 10K devices can be
configured on the board for the specific functionality required.
Table 6 shows FLEX 10K performance for some common designs. All
performance values were obtained with Synopsys DesignWare or LPM
functions. No special design technique was required to implement the
applications; the designer simply inferred or instantiated a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Notes:
(1)
The speed grade of this application is limited because of clock high and low specifications.
(2)
This application uses combinatorial inputs and outputs.
(3)
This application uses registered inputs and outputs.
Table 6. FLEX 10K & FLEX 10KA Performance
Application
Resources
Used
Performance
Units
LEs
EABs
-1 Speed
Grade
-2 Speed
Grade
-3 Speed
Grade
-4 Speed
Grade
16-bit loadable
counter (1)
16
0
204
166
125
95
MHz
16-bit accumulator (1)
16
0
204
166
125
95
MHz
16-to-1 multiplexer (2)
10
0
4.2
5.8
6.0
7.0
ns
256
× 8 RAM read
cycle speed (3)
0
1
172
145
108
84
MHz
256
× 8 RAM write
cycle speed (3)
01
106
89
68
63
MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 8-1624112-9 | INDUCTOR .18UH 5% 0603 |
| AGL1000V2-FGG484 | IC FPGA IGLOO 1.2-1.5V 484FPBGA |
| RW2-4809S/H2/B | CONV DC/DC 2W 36-72VIN 09VOUT |
| NCP512SQ50T1G | IC REG LDO 5V .2A SC70-5 |
| GEM10DSEN | CONN EDGECARD 20POS .156 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF10K30RC208-4N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Flex 10K 216 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K30RC240-3 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Flex 10K 216 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K30RC240-3N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Flex 10K 216 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K30RC240-4 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Flex 10K 216 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K30RC240-4N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Flex 10K 216 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。