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參數資料
| 型號： | EPF6016QC208-2N |
| 廠商： | Altera |
| 文件頁數： | 2/52頁 |
| 文件大小： | 0K |
| 描述： | IC FLEX 6000 FPGA 16K 208-PQFP |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 144 |
| 系列： | FLEX 6000 |
| LAB/CLB數： | 132 |
| 邏輯元件/單元數： | 1320 |
| 輸入/輸出數： | 171 |
| 門數： | 16000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 其它名稱： | 544-1953 EPF6016QC208-2N-ND |
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10
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Carry Chain
The carry chain provides a very fast (0.1 ns) carry-forward function
between LEs. The carry-in signal from a lower-order bit drives forward
into the higher-order bit via the carry chain, and feeds into both the LUT
and the next portion of the carry chain. This feature allows the FLEX 6000
architecture to implement high-speed counters, adders, and comparators
of arbitrary width. Carry chain logic can be created automatically by the
Altera software during design processing, or manually by the designer
during design entry. Parameterized functions such as LPM and
DesignWare functions automatically take advantage of carry chains for
the appropriate functions.
Because the first LE of each LAB can generate control signals for that LAB,
the first LE in each LAB is not included in carry chains. In addition, the
inputs of the first LE in each LAB may be used to generate synchronous
clear and load enable signals for counters implemented with carry chains.
Carry chains longer than nine LEs are implemented automatically by
linking LABs together. For enhanced fitting, a long carry chain skips
alternate LABs in a row. A carry chain longer than one LAB skips either
from an even-numbered LAB to another even-numbered LAB, or from an
odd-numbered LAB to another odd-numbered LAB. For example, the last
LE of the first LAB in a row carries to the second LE of the third LAB in
the row. In addition, the carry chain does not cross the middle of the row.
For instance, in the EPF6016 device, the carry chain stops at the 11th LAB
in a row and a new carry chain begins at the 12th LAB.
Figure 5 shows how an n-bit full adder can be implemented in n + 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. Although the register can be bypassed for simple adders,
it can be used for an accumulator function. Another portion of the LUT
and the carry chain logic generates the carry-out signal, which is routed
directly to the carry-in signal of the next-higher-order bit. The final
carry-out signal is routed to an LE, where it is driven onto the FastTrack
Interconnect.
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相關代理商/技術參數 |
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| EPF6016QC2083 | 制造商:ALTERA 功能描述:* |
| EPF6016QC208-3 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 6000 132 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6016QC208-3N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 6000 132 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6016QC240-2 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 6000 132 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6016QC240-2N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 6000 132 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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