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參數資料
| 型號： | FAN6920MRMY |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 20/24頁 |
| 文件大小： | 1490K |
| 描述： | IC PWM CTLR PFC/QUASI-RES 16SOP |
| 標準包裝： | 1 |
| 模式： | 臨界傳導（CRM） |
| 電流 - 啟動： | 20µA |
| 電源電壓： | 12 V ~ 25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOP |
| 包裝： | 標準包裝 |
| 其它名稱： | FAN6920MRMYDKR |
?2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6920MR " Rev. 1.0.8
20
V
D D - O N
V
D D - P W M - O F F
V
D D - O F F
G a t e
I
D D - P W M - O F F I
D D - S T
I
D D - O P
Figure 39. Typical Waveform of V
DD
Voltage and
Gate Signal at Hiccup Mode Operation
Green-Mode Operation and PFC-ON / OFF Control
(FB Pin)
Green mode further reduces power loss in the system
(e.g. switching loss). Through off-time modulation to
regulate switching frequency according to FB pin
voltage. When output loading decreases, FB voltage
lowers due to secondary feedback movement and the
t
OFF-MIN
is extended. After t
OFF-MIN
(determined by FB
voltage), the internal valley-detection circuit is activated
to detect the valley on the drain voltage of the PWM
switch. When the valley signal is detected, FAN6920MR
outputs a PWM gate signal to turn on the switch and
begin a new switching cycle.
With green mode operation and valley detection, at
light-load condition; the power system can perform
extended valley switching a DCM operation and can
further reduce switching loss for better conversion
efficiency. The FB pin voltage versus t
OFF-MIN
time
characteristic curve is shown in Figure 40. As Figure 40
shows, FAN6920MR can narrow down to 2.25 ms t
OFF
time, which is around 440 Hz switching frequency.
Referring to Figure 1 and Figure 2, FB pin voltage is not
only used to receive secondary feedback signal to
determine gate on-time, but also determines PFC stage
operating mode.
V
FB
t
O F F -M IN
2.25ms
20.5祍
1.2V(V
G
)
2.1V(V
N
)
5祍
PFC Burst
Mode
PFC On
V
CTRL-PFC
擵
CTRL
Figure 40. V
FB
Voltage vs. t
OFF-MIN
Time
Characteristic Curve
Valley Detection (DET Pin)
When FAN6920MR operates in Green Mode, t
OFF-MIN
is
determined by the Green Mode circuit, according to the
FB pin voltage level. After t
OFF-MIN
, the internal valley-
detection circuit is activated. During t
OFF
of the PWM
switch, when transformer inductor current discharges to
zero, the transformer inductor and parasitic capacitor of
PWM switch start to resonate concurrently. When the
drain voltage on the PWM switch falls, the voltage
across on auxiliary winding V
AUX
also decreases since
the auxiliary winding is coupled to the primary winding.
Once the V
AUX
voltage resonates and falls to negative,
V
DET
voltage is clamped by the DET pin (refer to Figure
41) and FAN6920MR is forced to flow out a current I
DET
.
FAN6920MR reflects and compares this I
DET
current. If
this source current rises to a threshold current, the
PWM gate signal is sent out after a fixed delay time
(200 ns typical).
0.3V
I
DET
Auxiliary
Winding
DET
FAN6920MR
+
V
AUX
-
+
V
DET
-
10
R
A
R
DET
Figure 41. Valley Detection
Figure 42. Measured Waveform of Valley Detection
High / Low Line Over-Power Compensation (DET Pin)
Generally, when the power switch turns off, there is a
delay from gate signal falling edge to power switch off.
This delay is produced by an internal propagation delay
of the controller and the turn-off delay of the PWM
switch due to gate resistor and gate-source capacitor
C
ISS
. At different AC input voltages, this delay produces
different maximum output power with the same PWM
current limit level. Higher input voltage generates higher
maximum output power because applied voltage on
primary winding is higher and causes higher rising slope
inductor current. It results in higher peak inductor
current at the same delay. Furthermore, under the same
output wattage, the peak switching current at high line is
lower than that at low line. Therefore, to make the
maximum output power close at different input voltages,
the controller needs to regulate V
LIMIT
voltage of the
CSPWM pin to control the PWM switch current.
Referring to Figure 43, during t
ON
of the PWM switch,
the input voltage is applied to primary winding and the
voltage across on auxiliary winding V
AUX
is proportional
to primary winding voltage. As the input voltage
increases, the reflected voltage on auxiliary winding
t
OFF
Start to
detect valley
I
det
flow out
from DET pin
Delay time and
then trigger
gate signal
Valley
switching
0V
0V
V
DET
OPWM
V
AUX
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