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參數資料
| 型號： | FAN6921MRMY |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 18/24頁 |
| 文件大小： | 1210K |
| 描述： | IC CTLR PFC/FLYBACK 16-SOICN |
| 標準包裝： | 2,500 |
| 模式： | 臨界傳導（CRM） |
| 電流 - 啟動： | 10µA |
| 電源電壓： | 8.5 V ~ 25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC N |
| 包裝： | 帶卷 (TR) |
?2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6921MR Rev. 1.0.4
18
PFC Peak Current Limiting (CSPFC pin)
During PFC stage switching operation, the PFC switch
current is detected by current-sense resistor on the
CSPFC pin and the detected voltage on this resistor is
delivered to input terminal of a comparator and
compared with a threshold voltage 0.82 V (typical).
Once the CSPFC pin voltage is higher than the
threshold voltage, PFC gate is turned off immediately.
The PFC peak switching current is adjustable by the
current-sense resistor. Figure 33 shows the measured
waveform of PFC gate and CSPFC pin voltage.
Figure 33. Cycle-by-Cycle Current Limiting
Brown-In / Out Protection (VIN Pin)
With AC voltage detection, FAN6921MR can perform
brown-in/ out protection (AC voltage UVP). Figure 34
shows the key operation waveforms of brown-in / out
protection. Both use the VIN pin to detect AC input
voltage level and the VIN pin is connected to AC input
by a resistor divider (refer to Figure 1); therefore, the
V
VIN
voltage is proportional to the AC input voltage.
When the AC voltage drops, and V
VIN
voltage is lower
than 1 V for 100 ms, the UVP protection is activated and
the COMP pin voltage is clamped to around 1.6 V.
Because PFC gate duty is determined by comparing
sawtooth waveform and COMP pin voltage, lower
COMP voltage results in narrow PFC on-time, so that
the energy converged is limited and the PFC output
voltage decreases. When INV pin is lower than 1.2 V,
FAN6921MR stops all PFC and PWM switching
operation immediately until V
DD
voltage drops to turn-off
voltage then raises to turn-on voltage again (UVLO).
When the brownout protection is activated, all switching
operation is turned off, V
DD
voltage enters hiccup mode
up and down continuously. Until V
VIN
voltage is higher
than 1.3 V (typical) and V
DD
reaches turn-on voltage
again, the PWM and PFC gate is sent out.
The measured waveforms of brown-in / out protection
are shown in Figure 35.
Figure 34. Operation Waveforms of Brown-In/ Out
Protection
Figure 35. Measured Waveform of Brown-In/ Out
Protection (Adapter Application)
OPFC
OPWM
AC Input
V
DD
V
DD
Hiccup Mode
Brownout
Brown-In
OPFC
CSPFC
PFC MOS Current Limit
0.82V
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