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參數資料
| 型號： | FAN6982MY |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 14/16頁 |
| 文件大小： | 547K |
| 描述： | IC CTLR PFC CCM 14-SOICN |
| 標準包裝： | 2,500 |
| 模式： | 連續導電（CCM） |
| 頻率 - 開關： | 50kHz ~ 75kHz |
| 電流 - 啟動： | 30µA |
| 電源電壓： | 11 V ~ 22 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC N |
| 包裝： | 帶卷 (TR) |
?2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6982 " Rev. 1.0.3
14
PFC Soft-Start Function
The FAN6982 PFC soft-start function is shown in
Figure 30. When bulk voltage is under the 96% of
setting voltage; V
EA
clamps to 2.8V, the output current
of multiplier cuts half, the rectifier line current is limited
by current loop, and PFC output rise time increases.
When bulk voltage is over 96%, the clamping function
is disabled, and the bulk voltage can be regulated by
voltage error amplifier.
There have two advantages with PFC soft-start: one is
the MOSFET experience of current is reduced, which
can obtain more de-rating with MOSFET current level.
The other one is to reduce the overshoot of PFC bulk
voltage at the rising time because the charge current
becomes small, the bulk voltage can not exceed to
setting voltage easily.
Figure 30. PFC Soft-Start
RDY Function
The FAN6982 RDY function, is shown in Figure 31, is
controlled by voltage of FBPFC. If the voltage of
FBPFC is over than 96% of 2.5V, the RDY pin is
connected to SGND. If the FBPFC is under the 46% of
2.5V, the RDY appears open-drain situation. Usually
the capacitor is parallel with the RDY pin to prevent the
layout noise.
The PNP transistor can control the AHB LLC or dual-
forward controller on the same side or the op-to to
control the LLC controller on the other side.
Figure 31. RDY Application Circuit
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