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參數(shù)資料
| 型號(hào)： | GAL16V8D-15LPNI |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 23/26頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PLD 8MACRO 5.0V 15NS 20PDIP |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | GAL®16V8 |
| 可編程類型： | EE PLD |
| 最大延遲時(shí)間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 宏單元數(shù)： | 8 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
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Specifications GAL16V8
4
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
are illustrated in the following pages. Two global bits, SYN and
AC0, control the mode configuration for all macrocells. The XOR
bit of each macrocell controls the polarity of the output in any of the
three modes, while the AC1 bit of each of the macrocells controls
the input/output configuration. These two global and 16 individ-
ual architecture bits define all possible configurations in a GAL16V8
. The information given on these architecture bits is only to give
a better understanding of the device. Compiler software will trans-
parently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.
The following is a list of the PAL architectures that the GAL16V8
can emulate. It also shows the OLMC mode under which the
GAL16V8 emulates the PAL architecture.
PAL Architectures
GAL16V8
Emulated by GAL16V8
Global OLMC Mode
16R8
Registered
16R6
Registered
16R4
Registered
16RP8
Registered
16RP6
Registered
16RP4
Registered
16L8
Complex
16H8
Complex
16P8
Complex
10L8
Simple
12L6
Simple
14L4
Simple
16L2
Simple
10H8
Simple
12H6
Simple
14H4
Simple
16H2
Simple
10P8
Simple
12P6
Simple
14P4
Simple
16P2
Simple
Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the soft-
ware to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 11 are permanently configured
as clock and output enable, respectively. These pins cannot be con-
figured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
Registered
Complex
Simple
Auto Mode Select
ABEL
P16V8R
P16V8C
P16V8AS
P16V8
CUPL
G16V8MS
G16V8MA
G16V8AS
G16V8
LOG/iC
GAL16V8_R
GAL16V8_C7
GAL16V8_C8
GAL16V8
OrCAD-PLD
"Registered"1
"Complex"1
"Simple"1
GAL16V8A
PLDesigner
P16V8R2
P16V8C2
P16V8A
TANGO-PLD
G16V8R
G16V8C
G16V8AS3
G16V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
Output Logic Macrocell (OLMC)
Compiler Support for OLMC
ALL
DEVICES
DISCONTINUED
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| GAL16V8D-15LR/833 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
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| GAL16V8D-15LS | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 16 INPUT 8 OUTPUT 5V LOW POWER 15ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| GAL16V8D-15QJ | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5V 16 I/O RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| GAL16V8D-15QJN | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 16 Input 8 Output 5V 1/4 Power 15ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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