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參數(shù)資料
| 型號(hào)： | GAL16V8D-15QPN |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 11/26頁 |
| 文件大小： | 0K |
| 描述： | IC PLD 8MACRO 5.0V 15NS 20PDIP |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | GAL®16V8 |
| 可編程類型： | EE PLD |
| 最大延遲時(shí)間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 宏單元數(shù)： | 8 |
| 工作溫度： | 0°C ~ 75°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
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Specifications GAL16V8
17
Typ. Vref = 3.2V
Typical Output
Typ. Vref = 3.2V
Typical Input
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Circuitry within the GAL16V8 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (
tpr, 1μs MAX). As a result,
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be-
cause of the asynchronous nature of system power-up, some
Vcc
PIN
Vcc
Vref
Active Pull-up
Circuit
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Vcc (min.)
tpr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
twl
tsu
conditions must be met to provide a valid power-up reset of the
device. First, the VCC rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of
tpr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.
Power-Up Reset
Input/Output Equivalent Schematics
ALL
DEVICES
DISCONTINUED
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GAL16V8D-20LD/833 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL16V8D-20LD/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| GAL16V8D-20LR/833 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL16V8D-20LR/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| GAL16V8D-20QJI | 功能描述:SPLD - 簡單可編程邏輯器件 16 INPUT 8 OUTPUT 5V LOW POWER 20ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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