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參數資料
| 型號： | GS816218BGB-200 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| 中文描述： | 1M X 18 CACHE SRAM, 6.5 ns, PBGA119 |
| 封裝： | ROHS COMPLIANT, FBGA-119 |
| 文件頁數： | 1/37頁 |
| 文件大小： | 866K |
| 代理商： | GS816218BGB-200 |
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GS816218/36B(B/D)
1M x 18, 512K x 36
18MbS/DCD Sync Burst SRAMs
250 MHz
–
150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
119-- & 165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.04 9/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/37
2004, GSI Technology
Features
FT pin for user-configurable flow through or pipeline operation
Single/Dual Cycle Deselect selectable
IEEE 1149.1 JTAG-compatible Boundary Scan
ZQ mode pin for user-selectable high/low output drive
2.5 V or 3.3 V +10%/–10% core power supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to SCD x18/x36 Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119-bump and 165-bump BGA packages
RoHs-compliant 119-bump and 165-bump BGA packages available
Functional Description
Applications
The GS816218/36B(B/D) is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although of a
type originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main store to
networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode . Holding the FT mode pin low places the RAM in
Flow Through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS816218/36B(B/D) is an SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers. DCD RAMs hold the deselect command for one full
cycle and then begin turning off their outputs just after the second
rising edge of clock. The user may configure this SRAM for either
mode of operation using the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
FLXDrive
The ZQ pin allows selection between high drive strength (ZQ low) for
multi-drop bus applications and normal drive strength (ZQ floating or
high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS816218/36B(B/D) operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250
-200
-150
Unit
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
2.5
4.0
3.0
5.0
3.8
6.7
ns
ns
295
345
245
285
200
225
mA
mA
Flow Through
2-1-1-1
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
225
255
200
220
185
205
mA
mA
相關PDF資料 |
PDF描述 |
|---|---|
| GS816218BGB-200I | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816218BGB-250 | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816218BGB-250I | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816218BGD-150I | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
| GS816218BGD-200 | 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS816218BGB-200I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 6.5NS/3NS 119FBGA - Trays |
| GS816218BGB-200IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 6.5NS/3NS 119FBGA - Trays |
| GS816218BGB-200V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 6.5NS/3NS 119FPBGA - Trays |
| GS816218BGB-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 18MBIT 1MX18 5.5NS/2.5NS 119FBGA - Trays |
| GS816218BGB-250I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 5.5NS/2.5NS 119FBGA - Trays |
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