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參數(shù)資料
| 型號： | GS864272C-167V |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
| 中文描述： | 1M X 72 CACHE SRAM, 8 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, BGA-209 |
| 文件頁數(shù)： | 1/35頁 |
| 文件大小： | 934K |
| 代理商： | GS864272C-167V |
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Preliminary
GS864218/36/72(B/C)-xxxV
4M x 18, 2M x 36, 1M x 72
72Mb S/DCD Sync Burst SRAMs
250 MHz
–
167 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
119- & 209-Pin BGA
Commercial Temp
Industrial Temp
Rev: 1.03 6/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/35
2004, GSI Technology
Features
FT pin for user-configurable flow through or pipeline operation
Single/Dual Cycle Deselect selectable
IEEE 1149.1 JTAG-compatible Boundary Scan
ZQ mode pin for user-selectable high/low output drive
1.8 V or 2.5 V core power supply
1.8 V or 2.5 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to SCD x18/x36 Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119- and 209-bump BGA package
RoHS-compliant 119- and 209-bump BGA packages available
Functional Description
Applications
The GS864218/36/72(B/C)-xxxV is a
75,497,472
-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS864218/36/72(B/C)-xxxV is a SCD (Single Cycle
Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous
SRAM. DCD SRAMs pipeline disable commands to the same
degree as read commands. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs begin
turning off their outputs immediately after the deselect command
has been captured in the input registers. DCD RAMs hold the
deselect command for one full cycle and then begin turning off
their outputs just after the second rising edge of clock. The user
may configure this SRAM for either mode of operation using the
SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Core and Interface Voltages
The GS864218/36/72(B/C)-xxxV operates on a 1.8 V or 2.5 V
power supply. All inputs are 1.8 V or 2.5 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise from
the internal circuits and are 1.8 V or 2.5 V compatible.
Parameter Synopsis
-250
-200
-167
Unit
Pipeline
3-1-1-1
t
KQ
)
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
3.0
4.0
3.0
5.0
3.5
6.0
ns
ns
340
410
520
6.5
6.5
245
280
370
290
350
435
7.5
7.5
220
250
315
260
305
380
8.0
8.0
210
240
300
mA
mA
mA
ns
ns
mA
mA
mA
Flow Through
2-1-1-1
相關PDF資料 |
PDF描述 |
|---|---|
| GS864272C-200IV | 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
| GS864272C-200V | 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
| GS864272C-250IV | 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
| GS864272C-250V | 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
| GS864272GC-167IV | 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS864272C-200 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 72MBIT 1MX72 7.5NS/3NS 209FBGA - Trays |
| GS864272C-200IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 72MBIT 1MX72 7.5NS/3NS 209BGA - Bulk |
| GS864272C-200V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 72MBIT 1MX72 7.5NS/3NS 209BGA - Bulk |
| GS864272C-250 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 72MBIT 1MX72 6.5NS/3NS 209FBGA - Trays |
| GS864272C-250I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 72MBIT 1MX72 6.5NS/3NS 209FBGA - Trays |
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