- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385329 > GS8642Z72GC-167I (GSI TECHNOLOGY) 72Mb Pipelined and Flow Through Synchronous NBT SRAM PDF資料下載
參數(shù)資料
| 型號： | GS8642Z72GC-167I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 1M X 72 ZBT SRAM, 8 ns, PBGA209 |
| 封裝： | 22 X 14 MM, 1 MM PITCH, ROHS COMPLIANT, BGA-209 |
| 文件頁數(shù)： | 28/34頁 |
| 文件大小： | 872K |
| 代理商： | GS8642Z72GC-167I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁第31頁第32頁第33頁第34頁
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
3.3 V Test Port Input High Voltage
V
IHJ3
2.0
V
DD3
+0.3
V
1
3.3 V Test Port Input Low Voltage
V
ILJ3
–
0.3
0.8
V
1
2.5 V Test Port Input High Voltage
V
IHJ2
0.6 * V
DD2
V
DD2
+0.3
V
1
2.5 V Test Port Input Low Voltage
V
ILJ2
–
0.3
0.3 * V
DD2
V
1
TMS, TCK and TDI Input Leakage Current
I
INHJ
–
300
1
uA
2
TMS, TCK and TDI Input Leakage Current
I
INLJ
–
1
100
uA
3
TDO Output Leakage Current
I
OLJ
–
1
1
uA
4
Test Port Output High Voltage
V
OHJ
1.7
—
V
5, 6
Test Port Output Low Voltage
V
OLJ
—
0.4
V
5, 7
Test Port Output CMOS High
V
OHJC
V
DDQ
– 100 mV
—
V
5, 8
Test Port Output CMOS Low
V
OLJC
—
100 mV
V
5, 9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Input Under/overshoot voltage must be
–
2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
V
ILJ
≤
V
IN
≤
V
DDn
0 V
≤
V
IN
≤
V
ILJn
Output Disable, V
OUT
= 0 to V
DDn
The TDO output driver is served by the V
DDQ
supply.
I
OHJ
=
–
4 mA
I
OLJ
= + 4 mA
I
OHJC
= –100 uA
I
OLJC
= +100 uA
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
28/34
2004, GSI Technology
JTAG Port AC Test Conditions
Notes:
1.
2.
Include scope and jig capacitance.
Test conditions as shown unless otherwise noted.
Parameter
Conditions
Input high level
V
DD
– 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V
DDQ
/2
Output reference level
V
DDQ
/2
DQ
V
DDQ
/2
50
30pF
*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8642Z72GC-200 | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642Z72GC-200I | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642Z72GC-250 | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642Z72GC-250I | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642Z72GC-300 | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8642Z72GC-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642Z72GC-200I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642Z72GC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 72MBIT 1MX72 6.5NS/3NS 209FBGA - Trays |
| GS8642Z72GC-250I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642Z72GC-300 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 72MBIT 1MX72 5.5NS/3NS 209FBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。