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參數資料
| 型號： | GS9020ACTVE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GENLINX -TM II GS9020A Serial Digital Video Input Processor |
| 中文描述： | GENLINX -商標二GS9020A串行數字視頻輸入處理器 |
| 文件頁數： | 6/31頁 |
| 文件大小： | 258K |
| 代理商： | GS9020ACTVE3 |
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6 of 31
G
27
A/D
I
Parallel port address/data bus control. When HIGH, the parallel port is used for address input.
When LOW, the parallel port is used for data input or output. In I2C mode, this pin must be set
LOW.
28
CS
I
Parallel port chip select. When CS is LOW and R/W is HIGH, the GS9020A drives the address/
data bus. When CS is LOW and R/W is LOW, the user should drive the address/data bus.
When CS is HIGH, the address/data bus is in a high impedance state (Hi - Z). In I2C mode, this
pin must be set HIGH.
31
RESET
I
Reset. When LOW, the internal control circuitry is reset.
32 - 35
STD[3:0]
O
Video standards indication as described in section 1.4
36 - 40
FL[4:0]
I/O
EDH flag data port to allow access to the EDH flags.
41, 42
S[1:0]
I/O
Control bits which select whether FF, AP, or ANC EDH flags are active on the EDH flag data
port (FL[4:0]). In FLAG_MAP mode, the S[1:0] pins become outputs (see device description).
43
F_R/W
I
Flag port read/write control. When HIGH, FL[4:0] are configured as outputs allowing EDH flags
to be read from the device. When LOW, FL[4:0] are configured as inputs allowing EDH flags to
be overwritten in the outgoing EDH packet. In FLAG_MAP mode this pin must be set HIGH.
44
INTERRUPT
O
Interrupt output. This output goes low when EDH errors occur. This pin is an open drain output
and requires an external pullup resistor. If this output is not used, a pullup resistor is not
required.
45
FLYWDIS
I
Flywheel disable. When HIGH, the internal flywheel is disabled. When LOW, the internal
flywheel is enabled.
46
NO_EDH
O
No EDH present indication. When HIGH, indicates EDH packets are not present in the
incoming data stream.
47
FIFO_RESET
O
FIFO Reset output. Asserted LOW during the TRSID word for composite standards and the
EAV or SAV word for component standards.
48
PCLKOUT
O
Parallel clock output.
52-60,49
DOUT[9:0]
O
Parallel digital video data outputs.
61
V
O
Vertical sync indication.
62
H
O
Horizontal sync indication.
63 - 65
F[2:0]
O
Field indication. F2 is the MSB.
66
FLAG_MAP
I
FLAG_MAP mode enable. When HIGH, FLAG_MAP mode is enabled.
When LOW, FLAG_MAP mode is disabled.
70, 71
SDO/SDO
O
Differential serial data outputs.
73
VBLANKS/L
I
Vertical blanking interval control. For NTSC signals, when VBLANKS/L is set LOW the 19 line
blanking interval is selected and when set HIGH the 9 line blanking interval is selected. For
PAL D2 signals, when VBLANKS/L is set LOW the 17 line blanking interval is selected and
when set HIGH the 7 line blanking interval is selected. For PAL component signals VBLANKS/L
should be set LOW.
74
BYPASS_EDH
I
Bypass EDH control. When HIGH, the device allows the EDH packet to pass through
unaltered.
75
SDOMODE
I
Serial data output control. When LOW, the serial data output is re-serialized processed data.
When HIGH, the serial data output is the looped through serial input. After changing
SDOMODE, the GS9020A must be reset for proper operation.
76
BLANK_EN
I
Blanking enable. When LOW, incoming data words are set to appropriate blanking levels.
77
ANC_CHKSM
I
Ancillary checksum updating enable. When HIGH, ancillary checksum updating is enabled.
PIN DESCRIPTIONS
NUMBER
SYMBOL
TYPE
DESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| GS9021A | GENLINX -TM II GS9021A EDH Coprocessor |
| GS9021ACFU | GENLINX -TM II GS9021A EDH Coprocessor |
| GS9022-CPJ | Digital Video Serializer |
| GS9022 | Digital Video Serializer |
| GS9022-CTJ | Digital Video Serializer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS9020-CFV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial Digital Video Input Processor |
| GS9020-CTV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial Digital Video Input Processor |
| GS9021 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:EDH Coprocessor |
| GS9021A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GENLINX -TM II GS9021A EDH Coprocessor |
| GS9021ACFU | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
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