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參數資料
| 型號： | GS9090 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI |
| 中文描述： | GS9090 GenLINX - R的第三270Mb / s的SDI和DVB解串器，意大利航天局 |
| 文件頁數： | 8/70頁 |
| 文件大小： | 696K |
| 代理商： | GS9090 |
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GS9090 Data Sheet
28201 - 1
July 2005
8 of 70
19
SDOUT_TDO
Synchronous
with
SCLK_TCK
Output
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Output / Test Data Output
Host Mode (JTAG/HOST = LOW):
SDOUT_TDO operates as the host interface serial output, SDOUT,
used to read status and configuration information from the internal
registers of the device.
JTAG Test Mode (JTAG/HOST = HIGH):
SDOUT_TDO operates as the JTAG test data output, TDO.
20
SDIN_TDI
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Input / Test Data Input
Host Mode (JTAG/HOST = LOW):
SDIN_TDI operates as the host interface serial input, SDIN, used to
write address and configuration information to the internal registers of
the device.
JTAG Test Mode (JTAG/HOST = HIGH):
SDIN_TDI operates as the JTAG test data input, TDI.
21, 29, 43
IO_VDD
Non
Synchronous
Input
Power
Power supply for digital I/O.
For a 3.3V tolerant I/O, connect pins to either +1.8V DC or +3.3V DC.
For a 5V tolerant I/O, connect pins to a +3.3V DC.
NOTE: For power sequencing requirements, see
Device Power Up on
page 64
.
22
DATA_ERROR
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT.
Signal levels are LVCMOS / LVTTL compatible.
The DATA_ERROR signal will be LOW when an error within the
received data stream has been detected by the device. This pin is an
inverted logical ‘OR’ing of all detectable errors listed in the internal
ERROR_STATUS register.
Once an error is detected, DATA_ERROR will remain LOW until the
start of the next video frame / field, or until the ERROR_STATUS
register is read via the host interface.
The DATA_ERROR signal will be HIGH when the received data stream
has been detected without error.
NOTE: It is possible to program which error conditions are monitored
by the device by setting appropriate bits in the ERROR_MASK register
HIGH. All error conditions are detected by default.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關PDF資料 |
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|---|---|
| GS9090-CNE3 | GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI |
| GS9092A | GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092ACNE3 | GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092 | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092-CNE3 | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS9090A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9090A GenLINX-R III 270Mb/s Deserializer for SDI |
| GS9090A_10 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GenLINX III 270Mb/s Deserializer |
| GS9090ACNE3 | 制造商:Semtech Corporation 功能描述:270Mb/s Deserializer 56-Pin QFN EP 制造商:Semtech Corporation 功能描述:270Mb/s Deserializer for SDI & ASI |
| GS9090B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GenLINX III 270Mb/s Deserializer for SDI |
| GS9090B_10 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GenLINX III 270Mb/s Deserializer for SDI |
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