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參數(shù)資料
| 型號(hào)： | ISPLSI 2032VE-300LTN48 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD ISP 32I/O 3NS 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | ispLSI® 2000VE |
| 可編程類(lèi)型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 3.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 8 |
| 宏單元數(shù)： | 32 |
| 門(mén)數(shù)： | 1000 |
| 輸入/輸出數(shù)： | 32 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | ISPLSI2032VE-300LTN48 |
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Specifications ispLSI 2032VE
11
Signal Descriptions
GOE 0
Global Output Enable input pin
Y0
Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs in the
device.
RESET/Y1
This pin performs two functions: (1) Active Low (0) Reset pin which resets all of the registers in the
device. (2) Dedicated Clock input.
BSCAN
Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a serial data input
pin to load programming data into the device. (2) When BSCAN is high, it functions as a dedicated input
pin.
TMS/NC1
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a mode control pin
for the Boundary Scan state machine. (2) When BSCAN is high, this pin is not to be connected to any
active signals, VCC or GND.
TDO/IN 1
Output/Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as an output
pin to read serial shift register data. (2) When BSCAN is high, it functions as a dedicated input pin.
TCK/Y2
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a clock pin for the
Boundary Scan state machine. (2) When BSCAN is high, it functions as a Dedicated Clock input.
GND
Ground (GND)
VCC
Vcc
NC1
No Connect
I/O
Input/Output pins – These are the general purpose I/O pins used by the logic array.
Signal Name
Description
GOE 0
40
2
43
A4
Y0
5
11
5
C1
RESET/Y1
29
35
31
D7
BSCAN
713
7D1
TDI/IN 0
8
14
8
E2
TMS/NC1
30
36
32
C6
TDO/IN 1
18
24
19
G4
TCK/Y2
27
33
29
E7
GND
17, 39
1, 23
18, 42
C4, E4
VCC
6, 28
12, 34
6, 30
D3, D5
NC1
—
12, 24, 36, 48
A1, A7, D4, G1, G7
Signal
44-Pin TQFP
44-Pin PLCC
48-Pin TQFP
49-Ball caBGA
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Locations
I/O Locations
Signal
44-Pin TQFP
44-Pin PLCC
48-Pin TQFP
49-Ball caBGA
I/O 0 - I/O 6
9, 10, 11, 12, 13, 14, 15
15, 16, 17, 18, 19, 20, 21
9, 10, 11, 13, 14, 15, 16
E1, F2, F1, E3, F3, G2, F4
I/O 7 - I/O 13
16, 19, 20, 21, 22, 23, 24
22, 25, 26, 27, 28, 29, 30
17, 20, 21, 22, 23, 25, 26
G3, F5, G5, F6, G6, E5, E6
I/O 14 - I/O 20
25, 26, 31, 32, 33, 34, 35
31, 32, 37, 38, 39, 40, 41
27, 28, 33, 34, 35, 37, 38
F7, D6, C7, B6, B7, C5, B5
I/O 21 - I/O 27
36, 37, 38, 41, 42, 43, 44
42, 43, 44, 3, 4, 5, 6
39, 40, 41, 44, 45, 46, 47
A6, B4, A5, B3, A3, B2, A2
I/O 28 - I/O 31
1, 2, 3, 4
7, 8, 9, 10
1, 2, 3, 4
C3, C2, B1, D2
SELECT
DEVICES
DISCONTINUED
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ispLSI2032VE-300LTN48 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2032VE300LTN48I | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| ISPLSI2032VL | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI-2032VL-110LB49 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI2032VL-110LB49 | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:2.5V In-System Programmable SuperFAST⑩ High Density PLD |
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