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參數資料
| 型號： | KM68V1000BLRI-7L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
| 中文描述： | 128K的× 8位低功耗和低電壓的CMOS Statinc內存 |
| 文件頁數： | 5/10頁 |
| 文件大小： | 183K |
| 代理商： | KM68V1000BLRI-7L |
KM68V1000B, KM68U1000B Family
CMOS SRAM
Revision 2.0
March 1998
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : C
L
=100pF+1TTL
C
L
=30pF+1TTL
AC CHARACTERISTICS
(Commercial product :T
A
=0 to 70
°
C, Extended product :T
A
=-25 to 85
°
C, Industrial product : T
A
=-40 to 85
°
C
KM68V1000B Family:Vcc=3.0~3.6V, KM68U1000B Family:Vcc=2.7~3.3V)
Parameter List
Symbol
Speed Bins
Units
70ns
100ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
70
-
100
-
ns
Address access time
t
AA
-
70
-
100
ns
Chip select to output
t
CO
-
70
-
100
ns
Output enable to valid output
t
OE
-
35
-
50
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
25
0
30
ns
Output disable to high-Z output
t
OHZ
0
25
0
30
ns
Output hold from address change
t
OH
10
-
15
-
ns
Write
Write cycle time
t
WC
70
-
100
-
ns
Chip select to end of write
t
CW
60
-
80
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
60
-
80
-
ns
Write pulse width
t
WP
55
-
70
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
25
0
30
ns
Data to write time overlap
t
DW
30
-
40
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
1. CS
≥
V
CC
-0.2V, CS
2
≥
V
CC
-0.2V(CS
1
controlled) or CS
2
≤
0.2V(CS
2
controlled)
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
1
1)
≥
Vcc-0.2V
2.0
-
3.6
V
Data retention current
I
DR
KM68V1000BL/L-L
Vcc=3.0V
CS
1
≥
Vcc-0.2V
CS
2
≥
Vcc-0.2V
or CS
2
≤
0.2V
Low Power
Low Low Power
-
-
1
0.5
30
15
μ
A
KM68V1000BLE/LE-L
KM68V1000BLI/LI-L
Low Power
Low Low Power
-
-
-
-
50
20
KM68U1000BL/L-L
Low Power
Low Low Power
-
-
-
-
25
10
KM68U1000BLE/LE-L
KM68U1000BLI/LI-L
Low Power
Low Low Power
-
-
-
-
25
15
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
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相關代理商/技術參數 |
參數描述 |
|---|---|
| KM68V1000BLT-10 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
| KM68V1000BLT-10L | 制造商:Samsung Semiconductor 功能描述:128K X 8 STANDARD SRAM, 100 ns, PDSO32 |
| KM68V1000BLT-7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
| KM68V1000BLT-7L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
| KM68V1000BLTE-10 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
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