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參數資料
| 型號： | LMC6572AIN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運算放大器 |
| 英文描述： | Low Voltage (2.7V and 3V) Operational Amplifier |
| 中文描述： | DUAL OP-AMP, 3500 uV OFFSET-MAX, 0.22 MHz BAND WIDTH, PDIP8 |
| 封裝： | DIP-8 |
| 文件頁數： | 8/13頁 |
| 文件大小： | 429K |
| 代理商： | LMC6572AIN |
Typical Performance Characteristics
V
S
= +3V, T
A
= 25C, Unless otherwise specified (Continued)
Applications Hints
1.0 LOW VOLTAGE AMPLIFIER TOPOLOGY
The LMC6574/2 incorporates a novel op-amp design topol-
ogy that enables it to maintain rail-to-rail output swing even
when driving a large load. Instead of relying on a push-pull
unity gain output buffer stage, the output stage is taken di-
rectly from the internal integrator, which provides both low
output impedance and large gain. Special feed-forward com-
pensation design techniques are incorporated to maintain
stability over a wider range of operating conditions than tra-
ditional micropower op-amps. These features make the
LMC6574/2 both easier to design with, and provide higher
speed than products typically found in this ultra-low power
class.
2.0 COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resis-
tance for amplifiers with ultra-low input current, like the
LMC6574/2.
Although the LMC6574/2 is highly stable over a wide range
of operating conditions, a large feedback resistor will react
even with small values of capacitance at the input of the
op-amp to reduce phase margin. The capacitance at the in-
put of the op-amp comes from transducers, photodiodes and
circuit board parasitics.
The effect of input capacitance can be compensated for by
adding a capacitor, C
f
, around the feedback resistors (as in
Figure 1) such that:
or
R
1
C
IN
≤
R
2
C
f
Since it is often difficult to know the exact value of C
, C
can
be experimentally adjusted so that the desired pulse re-
sponse is achieved. Refer to the LMC660 and LMC662 for a
more detailed discussion on compensating for input capaci-
tance.
When high input impedances are demanded, guarding of the
LMC6574/2 is suggested. Guarding input lines will not only
reduce leakage, but lowers stray input capacitance as well.
(See Printed-Circuit-Board Layout for High Impedance
Work).
3.0 CAPACITIVE LOAD TOLERANCE
Direct capacitive loading will reduce the phase margin of
many op-amps. A pole in the feedback loop is created by the
combination of the op-amp’s output impedance and the ca-
pacitive load. This pole induces phase lag at the unity-gain
crossover frequency of the amplifier resulting in either an os-
cillatory or underdamped pulse response. With a few exter-
nal components, op amps can easily indirectly drive capaci-
tive loads, as shown in Figure 2
In the circuit of Figure 2 R1 and C1 serve to counteract the
loss of phase margin by feeding the high frequency compo-
Bandwidth vs
Capacitive Load
DS011934-44
Capacitive Load
vs Phase Margin
DS011934-45
Capacitive Load
vs Gain Margin
DS011934-46
DS011934-6
FIGURE 1. Cancelling the Effect of Input Capacitance
DS011934-7
FIGURE 2. LMC6574/2 Noninverting Gain of 10
Amplifier, Compensated to Handle Capacitive Loads
www.national.com
8
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LMC6572BIM | 功能描述:運算放大器 - 運放 RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LMC6572BIM/NOPB | 功能描述:運算放大器 - 運放 RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LMC6572BIMM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage (2.7V and 3V) Operational Amplifier |
| LMC6572BIMMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage (2.7V and 3V) Operational Amplifier |
| LMC6572BIMX | 功能描述:運算放大器 - 運放 RoHS:否 制造商:STMicroelectronics 通道數量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
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