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參數(shù)資料
| 型號(hào)： | LMC6681AIMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)算放大器 |
| 英文描述： | Low Voltage, Rail-To-Rail Input and Output CMOS |
| 中文描述： | OP-AMP, 1000 uV OFFSET-MAX, 1.2 MHz BAND WIDTH, PDSO8 |
| 封裝： | SOP-8 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 750K |
| 代理商： | LMC6681AIMX |
3.0 Low Voltage Operation
(Continued)
Figure 6 shows an input voltage exceeding both supplies
with no resulting phase inversion on the output.
4.0 Capacitive Load Tolerance
The LMC6681/2/4 can typically drive a 100 pF load with V
S
= 10V at unity gain without oscillating. The unity gain fol-
lower is the most sensitive configuration to capacitive load.
Direct capacitive loading reduces the phase margin of
op-amps. The combination of the op-amp’s output imped-
ance and the capacitive load induces phase lag. This results
in either an underdamped pulse response or oscillation.
Capacitive load compensation can be accomplished using
resistive isolation as shown in Figure 7 If there is a resistive
component of the load in parallel to the capacitive compo-
nent, the isolation resistor and the resistive load create a
voltage divider at the output. This introduces a DC error at
the output.
Figure 8 displays the pulse response of the LMC6681 circuit
in Figure 7
Another circuit, shown in Figure 9 is also used to indirectly
drive capacitive loads. This circuit is an improvement to the
circuit shown Figure 7 because it provides DC accuracy as
well as AC stability. R1 and C1 serve to counteract the loss
of phase margin by feeding the high frequency component of
the output signal back to the amplifiers inverting input,
thereby preserving phase margin in the overall feedback
loop. The values of R1 and C1 should be experimentally de-
termined by the system designer for the desired pulse re-
sponse. Increased capacitive drive is possible by increasing
the value of the capacitor in the feedback loop.
DS012042-10
FIGURE 6. An Input Voltage Signal Exceeds
LMC6681/2/4 Power Supply Voltages of
V
S
= 1.8V with No Output Phase Inversion
DS012042-11
FIGURE 7. Resistive Isolation
of a 350 pF Capacitive Load
DS012042-12
FIGURE 8. Pulse Response of the
LMC6681 Circuit in
Figure 7
DS012042-13
FIGURE 9. The LMC6682 Compensated
to Ensure DC Accuracy and AC Stability
www.national.com
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMC6681AIN | Low Voltage, Rail-To-Rail Input and Output CMOS |
| LMC6681BIM | Low Voltage, Rail-To-Rail Input and Output CMOS |
| LMC6681BIN | Low Voltage, Rail-To-Rail Input and Output CMOS |
| LMC6682AIM | Low Voltage, Rail-To-Rail Input and Output CMOS |
| LMC6682AIMX | Low Voltage, Rail-To-Rail Input and Output CMOS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMC6681AIN | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage, Rail-To-Rail Input and Output CMOS |
| LMC6681B1MX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage, Rail-To-Rail Input and Output CMOS |
| LMC6681BIM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| LMC6681BIN | 制造商:Texas Instruments 功能描述: |
| LMC6682 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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