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參數資料
| 型號： | M2006-01-625.0000LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC36 |
| 封裝： | 9 X 9 MM, SMT-36 |
| 文件頁數： | 7/10頁 |
| 文件大小： | 911K |
| 代理商： | M2006-01-625.0000LF |
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
7
M2006-01
Prelimnary Specifications
Micro Networks
An Integrated Circuit Systems Company
INPUT FREQUENCY CHARACTERISTICS
Symbol
F
IN
Parameter
Input Frequency
Test Conditions
Min
0.3
Max
700
Units
MHz
DIF_CLK0, nDIF_CLK0
DIF_CLK1, nDIF_CLK1
S_CLOCK
REF_CLK
50
MHz
MHz
0.3 200
Note 1: Output termnatedwith50
toV
CC
–2.V
AC CHARACTERISTICS
Symbol
F
OUT
N
Parameter
Test Conditions
Min
75
Typ
Max
700
Units
Output Frequency
Single Side Band
Phase Noise
@ 622MHz
Jitter (RMS)
Output Duty Cycle
Output Rise Time
for output pairs
FOUT0, nFOUT0 &
FOUT1, nFOUT1
Output Fall Time
for output pairs
FOUT0, nFOUT0 &
FOUT1, nFOUT1
Setup Time
MHz
dBc/Hz
dBc/Hz
dBc/Hz
ps
%
ps
ps
ps
1kHz offset
10kHz offset
100kHz offset
Non-deterministic
1kHz offset
10kHz offset
100kHz offset
50kHz to 80MHz
-72
-94
-123
0.50
50
450
425
275
J (t)
odc
t
R
1
FOUT = 155MHz
FOUT = 311MHz
FOUT = 622MHz
20% to 80%, each
output of pair measured
is terminated into 50
load biased at Vcc-2V
20% to 80%, each
output of pair measured
is terminated into 50
load biased at Vcc-2V
350
325
200
550
500
350
(Note 1)
t
F
FOUT = 155MHz
FOUT = 311MHz
FOUT = 622MHz
350
325
200
450
425
275
550
500
350
ps
ps
ps
(Note 1)
t
S
S_DATA to S_CLK
S_CLK to S_LOAD
S_DATA to S_CLK
S_CLK to S_LOAD
5
5
5
5
ns
ns
ns
ns
ms
ns
ns
ns
t
H
Hold Time
t
LOCK
t
PW
PLL Lock Time
Input Pulse Width
100
S_LOAD
ADD_CLK
DROP_CLK
10
10
10
MTIE
Mean Time Interval Error
Compliant with GR-253-CORE
Note: The output frequencies of 155MHz, 311MHz and622MHz were chosenfor device characterizationas these are commonoptical network clock frequencies.
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