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參數(shù)資料
| 型號： | M24C16-DS6TP |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 7/25頁 |
| 文件大小： | 449K |
| 代理商： | M24C16-DS6TP |
7/25
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 7. Write Mode Sequences with WC=1 (data write inhibited)
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the Read/Write bit
(RW) reset to 0. The device acknowledges this, as
shown in
Figure 8.
, and waits for an address byte.
The device responds to the address byte with an
acknowledge bit, and then waits for the data byte.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10
th
bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal Write cycle is triggered. A Stop
condition at any other time slot does not trigger the
internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
and Serial Clock (SCL) are ignored, and the de-
vice does not respond to any requests.
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the ad-
dressed location is Write-protected, by Write Con-
trol (WC) being driven High (during the period from
the Start condition until the end of the address
byte), the device replies to the data byte with
NoAck, as shown in
Figure 7.
, and the location is
not modified. If, instead, the addressed location is
not Write-protected, the device replies with Ack.
The bus master terminates the transfer by gener-
ating a Stop condition, as shown in
Figure 8.
.
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If the addressed loca-
tion is Write-protected, by Write Control (WC) be-
ing driven High (during the period from the Start
S
S
Byte Write
DEV SEL
BYTE ADDR
DATA IN
WC
S
Page Write
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
WC
DATA IN 3
AI02803C
Page Write
(cont'd)
WC (cont'd)
S
DATA IN N
ACK
ACK
NO ACK
R/W
ACK
ACK
NO ACK
NO ACK
R/W
NO ACK
NO ACK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M24C16-DW3T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C16-DW3TG | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C16-DW3TP | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C16-DW6T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| M24C16-DW6TG | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M24C16-FCS5TP/S | 制造商:ST 功能描述:16K bit Serial IC Bus EEPROM 1.7V+-5.5V |
| M24C16-FDW6TP | 制造商:STMicroelectronics 功能描述:E-EPROM |
| M24C16-FMB5TG | 功能描述:電可擦除可編程只讀存儲器 2-wire 電可擦除可編程只讀存儲器 400 kHz Protocol RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M24C16-FMC5TG | 功能描述:電可擦除可編程只讀存儲器 Serial Eeprom 16Kbit 1.7V to 5.5V 400 kHz RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M24C16-FMC6TG | 制造商:STMicroelectronics 功能描述:E-EPROM |
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