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參數資料
| 型號： | MC34055DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 網絡接口 |
| 英文描述： | 5-V Battery-Backup Supervisors for RAM Retention 8-MSOP -40 to 85 |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PDSO24 |
| 封裝： | PLASTIC, SO-24 |
| 文件頁數： | 4/16頁 |
| 文件大?。?/td> | 280K |
| 代理商： | MC34055DW |
MC34055
4
MOTOROLA ANALOG IC DEVICE DATA
TIMING CHARACTERISTICS
(0
°
C
≤
TA
≤
70
°
C)
Characteristic
Symbol
Min
Typ
Max
Unit
TRANSMIT START TIMING
TX EN H to TX+/TX– Enable Time
tTXEN
tFDXD
tTXSS
tPRCM
tSkew T
tJitter T
tTXRX
–
–
75
ns
TX Data A/B to TX+/TX– Enable Time
–
–
75
ns
Steady State Propagation Delay of TX Data A/B to TX+/TX– Output
–
–
75
ns
Pre–Emphasis Pulse Width
45
–
55
ns
Transmitter Caused Edge Skew Between TX+ and TX–
–
–
2.0
ns
Transmitter Added Edge Jitter to TX+/TX– from TX Data A/B
–
–
4.0
ns
Steady–State Delay between the TX Data A/B Input to the RX Data
A/B Outputs for Normal Operation
–
–
50
ns
TX EN H Assert to RX EN H Assert Under Normal Operation
tDREL
–
–
50
ns
TRANSMIT STOP TIMING
Delay between TX EN H Low and TX+/TX– High
tTXDH
tXTRE
–
–
75
ns
TX EN H Assert/De–assert Delay from TX EN H to RX EN H
Assert/De–assert
–
–
400
ns
End of Packet Hold Time from Last TX Data A/B Edge or
TX EN H De–assert
tTDDC
250
–
–
ns
LINK BEAT PULSES
Output Link Test Pulse Width
tLKPW
tLDCY_A
80
–
120
ns
Minimum Link Beat Pulse Duration on RX+/RX–
80
–
192
ns
LOOP BACK MODE TIMING
Delay from Loop L Deassertion to RX EN H Driven from
TX EN H Status
tLTRA
–
–
30
ns
TX EN H Assert/De–assert to RX EN H, Assert/De–assert when in
Loop–Back Mode and Receiver Inactive
tLTRX
–
–
50
ns
Steady–State TX Data A/B to RX Data A/B when in Loop–Back Mode
tLTRD
–
–
50
ns
SMART SQUELCH
Interval Unit Squelch Deactivation
tSQ
–
–
5.0
Bit
Times
RECEIVE START TIMING
Receiver–Added Edge Skew to RX Data A/B Signal
tSkew R
tJitter R
tRXNE
tRARE
tRXSS
–
–
1.5
ns
Receiver–Added Edge Jitter to RX Data A/B Signal
–
–
1.5
ns
Start–Up Delay from RX+/RX– to RX Data A/B
–
–
50
ns
Delay from RX EN H Assertion Until RX Data A/B Valid
–10
–
+10
ns
Steady–State Propagation Delay from RX+/RX– Data A/B
–
–
50
ns
RECEIVE SHUTDOWN TIMING
Last received Data Edge until the RX EN H Output forces low
tRXDE
155
–
250
ns
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