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參數資料
| 型號： | MC44251 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Triple 8-Bit Video ADC Three-State Outputs |
| 中文描述： | 三8位視頻ADC的三態輸出 |
| 文件頁數： | 5/18頁 |
| 文件大小： | 273K |
| 代理商： | MC44251 |
MC44251
MOTOROLA
5
RESISTIVE REFERENCE NETWORK
RTOP (Pin 26)
RBOT (Pin 30)
RMID (Pin 28)
Taps on the reference ladder are pinned out, providing
access to the bottom (RBOT), the top (RTOP), and the middle
scale points. These pins are intended for ac bypassing as
ladder noise may present a problem. The value of the de-
coupling capacitor should not exceed 47 nF. Large capac-
itance values can cause problems because of the amount of
energy stored. When a system containing the MC44251 is
rapidly powered down and up, the capacitor voltage may
exceed the supply voltage during the power up and cause a
latch–up condition. Failure to adequately decouple these
pins can adversely affect the conversion process.
SUPPLY PINS
VDD(A) (Pin 34)
VDD(D) (Pins 44, 12)
VDD(R) (Pin 25)
The three types of supply pins are analog, digital, and
reference. The dc voltage applied to all four pins must be
maintained such that
VDD(A) = VDD(D) = VDD(R).
Each pin must be carefully decoupled to ground as close
to the package as possible, and particular care should be
taken with VDD(R) as any noise present on this pin will
appear in the output data as an equivalent input noise. This
noise will be present on the Rin, Gin, and Bin input pins in a
ratio of 1:1 to the input noise (worst case condition). Noise
reduction can be improved by incorporating choke coil induc-
tors in series with the power supply rails.
ANALOG INPUTS
Rin (Pin 27)
Gin (Pin 29)
Bin (Pin 31)
The analog signals to be converted are input at these pins.
An on–chip clamp circuit for dc restoration is available when
using ac coupling. The clamp circuit operation is activated by
the presence of the signal at the HZ input. This signal is
derived from the composite sync information and must be
coincident with the horizontal sync of the composite video
waveform for proper operation. Yin, Uin, and Vin may be used
instead of the RGB signals. In this case the conversion will
be a YUV analog–to–digital conversion.
Ibias (Pin 33)
The comparator bias current is set by connecting an exter-
nal resistor between Ibias and ground. The conversion rate is
guaranteed for a resistor value of 5.1 k
±
5% and will
decrease logarithmically with increased resistance. The
resistor must be placed adjacent to the Ibias pin. No decoup-
ling capacitor is allowed on this pin.
DIGITAL OUTPUTS
R0 – R7 (Pins 11, 13 – 15, 18 – 21)
G0 – G7 (Pins 2 – 5, 7 – 10)
B0 – B7 (Pins 36 – 39, 41 – 43, 1)
These pins are the parallel output for the digital value for
the RGB signals. R0 through R7 are the digital equivalent of
the analog RED input, G0 through G7 are equivalent to the
GREEN input, and B0 through B7 are equivalent to the BLUE
input. If YUV analog signals have been input instead of the
RGB signals; the digital outputs will be Y0 through Y7, U0
through U7, and V0 through V7.
DIGITAL INPUTS
Clock (Pin 17)
The analog input voltages to be converted are sensed at
the falling edge of the clock signal and the corresponding
data is present on the digital outputs at the clock signal rising
edge, 2.5 cycles later (see Figure 2).
HZ (Pin 23)
This is the horizontal synchronization input, and is used to
increment the dither generator. The clamp network is also
controlled by HZ to ensure proper dc restoration for Rin, Gin,
and Bin before conversion. Schmitt trigger input is included to
improve noise immunity.
VTN (Pin 24)
The vertical synchronization input, VTN, resets the dither
generator after every second vertical sync pulse (after each
frame). Schmitt trigger input is included to improve noise
immunity.
MODE (Pin 35)
This pin is used to select the proper clamp levels (see
Table 1).
CHIP SELECT (Pin 6)
Chip select is an active low input used to enable the ADC
for data transfers. When the CS is at a high level, the digital
output is forced to a high impedance state.
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