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參數資料
| 型號： | SI3500-A-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數： | 10/18頁 |
| 文件大小： | 192K |
| 描述： | IC POE SWITCH PWR OVER LAN 20QFN |
| 標準包裝： | 60 |
| 類型： | 以太網供電開關（PoE） |
| 應用： | IP 電話，LAN 網絡供電，網絡路由器和交換機 |
| 內部開關： | 是 |
| 電流限制： | 525mA |
| 電源電壓： | 42 V ~ 57 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VQFN 裸露焊盤 |
| 供應商設備封裝： | 20-QFN（5x5） |
| 包裝： | 管件 |
| 配用： | SMARTPSE24-KIT-ND - KIT EVAL REF 24PORT SPI/UART SI3480MS8-KIT-ND - KIT EVAL 8PORT SI3480/52/SI3500 |
| 其它名稱： | 336-1844-5 |
Si3500
10
Rev. 1.1
for isolated applications) is also routed into the PWM
and determines the slicing of the oscillator.
The PWM controls the switching FET drive circuitry. A
significant advantage of integrating the switching power
FET onto the same monolithic IC as the switching
regulator controller is the ability to precisely adjust the
drive strength and timing to the FET's sizable gate,
resulting in high regulator efficiency. Furthermore,
current-limiting circuitry prevents the switching FET
from sinking too much current, dissipating too much
power, and becoming damaged. Thermal overload
protection provides a secondary level of protection.
The flexibility of the Si3500's switching regulator allows
the system designer to realize either the isolated or non-
isolated application circuitry using a single device. In
operation, the integration of the switching FET allows
tighter control and more efficient operation than a
general-purpose switching regulator coupled with a
general-purpose external FET.
4. Layout Guidelines
The following are general PCB layout considerations;
reference designs are also available. Due to the unique
high-voltage and high-power design considerations,
Silicon Labs recommends that the reference designs be
followed closely for both BOM and layout. Visit the
Silicon Labs Technical Support web page and register to
submit a technical support request, particularly if you
are not closely following the recommended reference
design.
Care must be taken to connect the thermal pad of the
Si3500 to an appropriate heat spreader. For full-power
applications, a 2 square in plane with at least 9 thermal
vias is recommended. This heat spreader must be
electrically connected to the negative input power
supply.
Care must also be taken in layout to avoid EMI and
EMC. Input and output filter capacitors are normally
ceramic capacitors for high-frequency performance in
parallel with electrolytic capacitors for load transient
performance. The ceramic capacitors in particular
should be placed so as to minimize radiation for the
high-current paths of the switching regulator. The
circular area of current flow with the FET on and FET off
should be minimized. The direction of current flow with
FET on and FET off should maintain a constant
clockwise or counterclockwise rotation.
For EMI reduction, a 4 layer design with inner layers
connected to the positive input and Vss (for isolated
applications) or Vout (for non-isolated applications) is
recommended. The high-current paths should not flow
through these shield planes. Connection of the dc-to-dc
converter high-current paths to the shield plane should
be at a single point. Refer to the Si3452 reference
design databases for additional layout guideline details.
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