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參數(shù)資料
| 型號(hào)： | TMJ320C6211GGP167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 17/83頁(yè) |
| 文件大?。?/td> | 1176K |
| 代理商： | TMJ320C6211GGP167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
interrupt sources and interrupt selector
The C62x DSP core supports 16 prioritized interrupts, which are listed in Table 16. The highest-priority interrupt
is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00
INT_03) are non-maskable and fixed. The remaining interrupts (INT_04
INT_15) are maskable and
default to the interrupt source specified in Table 16. The interrupt source for interrupts 4
15 can be programmed
by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control
registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
Table 16. C6211/C6211B DSP Interrupts
INTERRUPT
SELECTOR
CONTROL
REGISTER
MUXL[4:0]
00100
MUXL[9:5]
00101
MUXL[14:10]
00110
MUXL[20:16]
00111
MUXL[25:21]
01000
MUXL[30:26]
01001
MUXH[4:0]
00011
MUXH[9:5]
01010
MUXH[14:10]
01011
MUXH[20:16]
00000
MUXH[25:21]
00001
MUXH[30:26]
00010
01100
01101
01110
01111
10000
11111
CPU
INTERRUPT
NUMBER
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT
INTERRUPT SOURCE
INT_00
INT_01
INT_02
INT_03
INT_04
INT_05
INT_06
INT_07
INT_08
INT_09
INT_10
INT_11
INT_12
INT_13
INT_14
INT_15
RESET
NMI
Reserved
Reserved
EXT_INT4
EXT_INT5
EXT_INT6
EXT_INT7
EDMA_INT
Reserved
SD_INT
Reserved
Reserved
DSP_INT
TINT0
TINT1
XINT0
RINT0
XINT1
RINT1
Reserved
Reserved. Do not use.
Reserved. Do not use.
External interrupt pin 4
External interrupt pin 5
External interrupt pin 6
External interrupt pin 7
EDMA channel (0 through 15) interrupt
None, but programmable
EMIF SDRAM timer interrupt
None, but programmable
None, but programmable
Host-port interface (HPI)-to-DSP interrupt
Timer 0 interrupt
Timer 1 interrupt
McBSP0 transmit interrupt
McBSP0 receive interrupt
McBSP1 transmit interrupt
McBSP1 receive interrupt
Reserved. Do not use.
Interrupts INT_00 through INT_03 are non-maskable and fixed.
Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control
registers fields. Table 16 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed
information on interrupt sources and selection, see the
TMS320C6000 DSP Interrupt Selector Reference Guide
(literature
number SPRU646).
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