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參數資料
| 型號： | TS80C31X2-VCED |
| 廠商： | TEMIC SEMICONDUCTORS |
| 英文描述： | 603R REV2.1 HIP3.0 ROHS |
| 中文描述： | 8位CMOS微控制器0-60兆赫 |
| 文件頁數： | 28/40頁 |
| 文件大小： | 484K |
| 代理商： | TS80C31X2-VCED |
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28
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
7.3 DC Parameters for Low Voltage
T
A
= 0
°
C to +70
°
C; V
SS
= 0 V; V
CC
= 2.7 V to 5.5 V
±
10%; F = 0 to 30 MHz.
T
A
= -40
°
C to +85
°
C; V
SS
= 0 V; V
CC
= 2.7 V to 5.5 V
±
10%; F = 0 to 30 MHz.
Table 15. DC Parameters for Low Voltage
NOTES
1.
V
IH
= V
CC
- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V
CC
. I
CC
would be slightly higher if a crystal oscillator used..
2.
Idle I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns, V
IL
= V
SS
+ 0.5 V, V
IH
= V
CC
- 0.5 V; XTAL2
N.C; Port 0 = V
CC
; EA = RST = V
SS
(see Figure 10.).
3.
Power Down I
CC
is measured with all output pins disconnected; EA = V
SS
, PORT 0 = V
CC
; XTAL2 NC.; RST = V
SS
(see Figure 11.).
4.
Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
OL
s of ALE and Ports 1 and 3. The noise is
due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi V
OL
peak 0.6V. A Schmitt Trigger use is not necessary.
5.
Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6.
Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin: 10 mA
Maximum I
OL
per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I
OL
for all output pins: 71 mA
IfI
OL
exceedsthetestcondition,V
OL
mayexceedtherelatedspecification.Pinsarenotguaranteedtosinkcurrentgreaterthanthelistedtestconditions.
7.
For other values, please contact your sales office.
Operating I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns (see Figure 12.), V
IL
= V
SS
+ 0.5 V,
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
V
IL
Input Low Voltage
-0.5
0.2 V
CC
- 0.1
V
V
IH
Input High Voltage except XTAL1, RST
0.2 V
CC
+ 0.9
V
CC
+ 0.5
V
V
IH1
Input High Voltage, XTAL1, RST
0.7 V
CC
V
CC
+ 0.5
V
V
OL
Output Low Voltage, ports 1, 2, 3
(6)
0.45
V
I
OL
= 0.8 mA
(4)
V
OL1
Output Low Voltage, port 0, ALE, PSEN
(6)
0.45
V
I
OL
= 1.6 mA
(4)
V
OH
Output High Voltage, ports 1, 2, 3
0.9 V
CC
V
I
OH
= -10
μ
A
V
OH1
Output High Voltage, port 0, ALE, PSEN
0.9 V
CC
V
I
OH
= -40
μ
A
I
IL
Logical 0 Input Current ports 1, 2 and 3
-50
μ
A
Vin = 0.45 V
I
LI
Input Leakage Current
±
10
μ
A
0.45 V < Vin < V
CC
I
TL
Logical 1 to 0 Transition Current, ports 1, 2, 3
-650
μ
A
Vin = 2.0 V
R
RST
RST Pulldown Resistor
50
90
(5)
200
k
CIO
Capacitance of I/O Buffer
10
pF
Fc = 1 MHz
T
A
= 25
°
C
I
PD
Power Down Current
TBD
(5)
TBD
μ
A
V
CC
= 2.0 V to 5.5 V
(3)
I
CC
Power Supply Current
(7)
Active Mode 16MHz
Idle Mode
16MHz
TBD
(5)
TBD
(5)
TBD
TBD
mA
mA
V
CC
= 3.3 V
(1)
V
CC
= 3.3 V
(2)
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