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參數資料
| 型號： | TS80C31X2-VLER |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit CMOS Microcontroller ROMless |
| 中文描述： | 8-BIT, 40 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 1.40 MM HEIGHT, VQFP-44 |
| 文件頁數： | 16/40頁 |
| 文件大小： | 484K |
| 代理商： | TS80C31X2-VLER |
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16
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
Table 5. SCON Register
SCON - Serial Control Register (98h)
7
Reset Value = 0000 0000b
Bit addressable
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
Bit
Mnemonic
Description
7
FE
Framing Error bit (SMOD0=1
)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
6
SM1
Serial port Mode bit 1
SM1
SM0
Mode
Description
Baud Rate
0
0
1
1
0
1
0
1
0
1
2
3
Shift Register
8-bit UART
9-bit UART
9-bit UART
F
XTAL
/12
Variable
F
XTAL
/64 or F
XTAL
/32
Variable
5
SM2
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.
4
REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3
TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2
RB8
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1
TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
0
RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 5. and Figure 6. in the other modes.
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