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參數資料
| 型號： | W39V080ATZ |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 1M 】 8 CMOS FLASH MEMORY WITH LPC INTERFACE |
| 中文描述： | 1M X 8 FLASH 3.3V PROM, 11 ns, PDSO40 |
| 封裝： | 10 X 20 MM, LEAD FREE, TSOP-40 |
| 文件頁數： | 5/34頁 |
| 文件大小： | 287K |
| 代理商： | W39V080ATZ |
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W39V080A
Publication Release Date: Dec. 28, 2005
- 5 -
Revision A4
6. FUNCTIONAL DESCRIPTION
6.1 Interface Mode Selection and Description
This device can be operated in two interface modes, one is Programmer interface mode, and the
other is LPC interface mode. The MODE pin of the device provides the control between these two
interface modes. These interface modes need to be configured before power up or return from
#RESET
.
When MODE pin is set to high position, the device is in the Programmer mode; while the
MODE pin is set to low position, it is in the LPC mode. In Programmer mode, this device just behaves
like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed.
The row address is mapped to the higher internal address A[19:11]. And the column address is
mapped to the lower internal address A[10:0]. For LPC mode, It complies with the LPC Interface
Specification Revision 1.1 Through the LAD[3:0] and #LFRAME
to communicate with the system
chipset .
6.2 Read (Write) Mode
In Programmer interface mode, the read(write) operation of the W39V080A is controlled by #OE
(#WE). The #OE (#WE) is held low for the host to obtain (write) data from(to) the outputs(inputs).
#OE is the output control and is used to gate data from the output pins. The data bus is in high
impedance state when #OE is high. As in the LPC interface the “bit 1 of CYCLE TYPE+DIR”
determines mode, the read or write. Refer to the timing waveforms for further details.
6.3 Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the
device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all
outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device
will return to read or standby mode, it depends on the control signals.
6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There is a hardware method to protect the top boot block and other sectors. Before power on
programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased.
If #WP pin is tied to low state before power on, the other sectors will not be programmed/erased.
In order to detect whether the boot block feature is set on or not, users can perform software
command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address
FFFF2(hex). You can check the DQ2/DQ3 at the address FFFF2 to see whether the #TBL/#WP pin is
in low or high state. If the DQ2 is “0”, it means the #TBL pin is tied to high state. In such condition,
whether boot block can be programmed/erased or not will depend on software setting. On the other
hand, if the DQ2 is “1”, it means the #TBL pin is tied to low state, then boot block is locked no matter
how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is “0”, it
means the #WP pin is in high state, then all the sectors except the boot block can be
programmed/erased. On the other hand, if the DQ3 is “1”, then all the sectors except the boot block
are programmed/erased inhibited.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
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相關代理商/技術參數 |
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| W39V080FA | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 8 CMOS FLASH MEMORY WITH FWH INTERFACE |
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| W39V080FAQZ | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M 】 8 CMOS FLASH MEMORY WITH FWH INTERFACE |
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