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參數資料
| 型號： | W3EG128M72ETSU403JD3 |
| 英文描述： | 1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| 中文描述： | 1GB的- 128Mx72 DDR SDRAM的無緩沖ECC瓦特/鎖相環 |
| 文件頁數： | 6/14頁 |
| 文件大小： | 277K |
| 代理商： | W3EG128M72ETSU403JD3 |
W3EG128M72ETSU-D3
-JD3
-AJD3
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2005
Rev. 0
I
DD1
: OPERATING CURRENT : ONE BANK
1. Typical Case : V
CC
=2.5V, T=25°C
2. Worst Case : V
CC
=2.7V, T=10°C
3. Only one bank is accessed with t
RC
(min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I
OUT
= 0mA
4. Timing Patterns :
DDR200 (100 MHz, CL=2) : t
CK=
10ns, CL2,
BL=4, t
RCD=
2*t
CK
, t
RAS=
5*t
CK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
DDR266 (133MHz, CL=2.5) : t
CK=
7.5ns,
CL=2.5, BL=4, t
RCD=
3*t
CK
, t
RC=
9*t
CK
, t
RAS=
5*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : t
CK
=7.5ns, CL=2,
BL=4, t
RCD
=3*t
CK
, t
RC
=9*t
CK
, t
RAS
=5*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR333 (166MHz, CL=2.5) : t
CK
=6ns, BL=4,
t
RCD
=10*t
CK
, t
RAS
=7*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR400 (200MHz, CL=3) : t
CK
=5ns, BL=4,
t
RCD
=15*t
CK
, t
RAS
=7*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
I
DD7A
: OPERATING CURRENT : FOUR BANKS
1. Typical Case : V
CC
=2.5V, T=25°C
2. Worst Case : V
CC
=2.7V, T=10°C
3. Four banks are being interleaved with t
RC
(min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
DDR200 (100 MHz, CL=2) : t
CK
=10ns, CL2,
BL=4, t
RRD
=2*t
CK
, t
RCD
=3*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL=2.5) : t
CK
=7.5ns,
CL=2.5, BL=4, t
RRD
=3*t
CK
, t
RCD
=3*t
CK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR266 (133MHz, CL=2) : t
CK
=7.5ns, CL2=2,
BL=4, t
RRD
=2*t
CK
, t
RCD
=2*t
CK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR333 (166MHz, CL=2.5) : t
CK
=6ns,
BL=4, t
RRD
=3*t
CK
, t
RCD
=3*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR400 (200MHz, CL=3) : t
CK
=5ns,
BL=4, t
RRD
=10*t
CK
, t
RCD
=15*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DETAILED TEST CONDITIONS FOR DDR SDRAM I
DD1
& I
DD7A
Legend : A = Activate, R = Read, W = Write, P = Precharge,
N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W3EG128M72ETSU-AJD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG128M72ETSU-D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG128M72ETSU-JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG2128M64ETSR263JD3XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx64 DDR SDRAM REGISTERED w/PLL |
| W3EG2128M64ETSR265JD3XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx64 DDR SDRAM REGISTERED w/PLL |
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