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參數資料
| 型號： | W3EG2256M72ASSR202JD3XG |
| 英文描述： | 4GB - 2x256Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| 中文描述： | 4GB的- 2x256Mx72 ECC的DDR SDRAM的注冊，瓦特/鎖相環 |
| 文件頁數： | 6/14頁 |
| 文件大?。?/td> | 230K |
| 代理商： | W3EG2256M72ASSR202JD3XG |
W3EG2256M72ASSR-JD3
-AJD3
PRELIMINARY
6
White Electronic Designs
November, 04
Rev. 3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0°C
≤
T
A
≤
+70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V.
Includes PLL and register power
Parameter
Operating Current
Symbol
I
DD0
Rank 1
Conditions
One device bank; Active - Precharge; t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and
control inputs changing once every two cycles.
One device bank; Active-Read-Precharge Burst
= 2; t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN); l
OUT
= 0mA;
Address and control inputs changing once per
clock cycle.
All device banks idle; Power-down mode; t
CK
=
t
CK
(MIN); CKE = (low)
CS# = High; All device banks idle;
t
CK
= t
CK
(MIN); CKE = High; Address and other
control inputs changing once per clock cycle. V
IN
= V
REF
for DQ, DQS and DM.
One device bank active; Power-Down mode; t
CK
(MIN); CKE = (low)
CS# = High; CKE = High; One device bank;
Active-Precharge;t
RC
= t
RAS
(MAX); t
CK
= t
CK
(MIN); DQ, DM and DQS inputs changing twice
per clock cycle; Address and other control inputs
changing once per clock cycle.
Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; t
CK
= t
CK
(MIN); l
OUT
= 0mA.
Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; t
CK
= t
CK
(MIN); DQ,DM and
DQS inputs changing once per clock cycle.
t
RC
= t
RC
(MIN)
CKE
≤
0.2V
Four bank interleaving Reads (BL=4) with auto
precharge with t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN);
Address and control inputs change only during
Active Read or Write commands.
DDR266:@CL=2, 2.5
Max
5265
DDR200@CL=2
Max
4815
Units
mA
Rank 2
Standby
State
I
DD3N
Operating Current
I
DD1
5895
5445
mA
I
DD3N
Precharge Power-
Down Standby Current
Idle Standby Current
I
DD2P
360
360
rnA
I
DD2P
I
DD2F
2650
2470
mA
I
DD2F
Active Power-Down
Standby Current
Active Standby Current
I
DD3P
1260
1080
mA
I
DD3P
I
DD3N
2110
1930
mA
I
DD3N
Operating Current
I
DD4R
6345
5805
mA
I
DD3N
Operating Current
I
DD4W
6525
5985
rnA
I
DD3N
Auto Refresh Current
Self Refresh Current
Operating Current
I
DD5
I
DD6
I
DD7A
8540
599
11835
8180
599
10935
mA
mA
mA
I
DD3N
I
DD6
I
DD3N
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相關代理商/技術參數 |
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|---|---|
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