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參數(shù)資料
| 型號： | W3EG72126S263AJD3 |
| 英文描述： | 1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| 中文描述： | 1GB的，128Mx72 ECC的DDR SDRAM的注冊瓦特/鎖相環(huán) |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 351K |
| 代理商： | W3EG72126S263AJD3 |
White Electronic Designs
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
November 2004
Rev. 3
Notes
1.
2.
All voltages referenced to V
SS
Tests for AC timing, I
DD
, and electrical AC and DC characteristics
may be conducted at normal reference / supply voltage levels, but
the related specifications and device operations are guaranteed for
the full voltage range specified.
Outputs are measured with equivalent load:
3.
4.
Output
(V
OUT
)
Reference
Point
30pF
50
V
TT
AC timing and I
DD
tests may use a V
IL
-to-V
IH
swing of up to 1.5V
in the test environment, but input timing is still referenced to V
REF
(or to the crossing point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between V
IL
(AC) and V
IH
(AC).
The AC and DC input level specifications are defined in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).
For slew rates less than 1V/ns and greater than or equal to 0.5V/
ns. If the slew rate is less than 0.5V/ns, timing must be derated: t
IS
has an additional 50ps per each 100mV/ns reduction in slew rate
from the 500mV/ns. t
IH
has 0ps added, that is, it remains constant.
If the slew rate exceeds 4.5V/ns, functionality is uncertain. For
335, slew rates must be greater than or equal to 0.5V/ns.
Inputs are not recognized as valid until V
REF
stabilizes. Exception:
during the period before V
REF
stabilizes, CKE
≤
0.3 x V
CCQ
is
recognized as LOW.
t
HZ
and t
LZ
transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).
The intent of the “Don’t Care” state after completion of the
postamble is the DQS-driven signal should either be HIGH, LOW,
or high-Z, and that any signal transition within the input switching
region must follow valid input requirements. That is, if DQS
transitions HIGH (above V
IHDC
(MIN) then it must not transition
LOW (below V
IHDC
) prior to t
DQSH
(MIN).
This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
5.
6.
7.
8.
9.
10.
11.
It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
high during this time, depending on t
DQSS
.
The refresh period is 64ms. This equates to an average refresh
rate of 7.8125μs. However, an AUTO REFRESH command must
be asserted at least once every 70.3μs; burst refreshing or posting
by the DRAM controller greater than eight refresh cycles is not
allowed.
The valid data window is derived by achieving other specifications
- t
HP
(t
CK/2
), t
DQSQ
, and t
QH
(t
QH
= t
HP
- t
QHS
). The data valid
window derates directly proportional with the clock duty cycle
and a practical data valid window can be derived. The clock is
allowed a maximum duty cycled variation of 45/55. Functionality
is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.
Referenced to each output group: x4 = DQS with DQ0-DQ3.
READs and WRITEs with auto precharge are not allowed to be
issued until t
RAS
(MIN) can be satisfied prior to the internal precharge
command being issued.
JEDEC specifies CK and CK# input slew rate must be > 1V/ns
(2V/ns differentially).
DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to t
DS
and t
DH
for
each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.
t
HP
min is the lesser of t
CL
min and t
CH
min actually applied to the
device CK and CK# inputs, collectively during bank active.
t
HZ
(MAX) will prevail over the t
DQSCK
(MAX) + t
RPST
(MAX)
condition. t
LZ
(MIN) will prevail over t
DQSCK
(MIN) + PRE (MAX)
condition.
For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.
CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until t
RFC
has been satisfied.
Whenever the operating frequency is altered, not including jitter,
the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG72126S263D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72126S263JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72126S265AJD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72126S265D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
| W3EG72126S265JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL |
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