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參數資料
| 型號： | W3EG72255S-JD3 |
| 英文描述： | 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| 中文描述： | 2GB的- 2x128Mx72 ECC的DDR SDRAM的注冊，瓦特/鎖相環 |
| 文件頁數： | 9/15頁 |
| 文件大小： | 260K |
| 代理商： | W3EG72255S-JD3 |
W3EG72255S-D3
-JD3
-AJD3
PRELIMINARY
9
White Electronic Designs
November 2004
Rev. 2
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
0°C ≤ T
A
≤ +70°C; V
CC
= +2.5V ±0.2V, V
CCQ
= +2.5V ±0.2V
AC Characteristics
335
262/263/265
202
Parameter
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to V
CC
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
Symbol
t
RCD
t
RP
t
RPRE
t
RPST
t
RRD
t
WPRE
t
WPRES
t
WPST
t
WR
t
WTR
NA
t
REFC
t
REFI
t
VTD
t
XSNR
t
XSRD
Min
15
15
0.9
0.4
12
0.25
0
0.4
15
1
Max
Min
15
15
0.9
0.4
15
0.25
0
0.4
15
1
Max
Min
15
15
0.9
0.4
15
0.25
0
0.4
15
1
Max
Units
ns
ns
t
CK
t
CK
ns
t
CK
ns
t
CK
ns
t
CK
ns
μs
μs
ns
ns
t
CK
Notes
1.1
0.6
1.1
0.6
1.1
0.6
19
10,11
9
0.6
0.6
0.6
t
QH
-t
DQSQ
t
QH
-t
DQSQ
t
QH
-t
DQSQ
13
12
12
70.3
7.8
70.3
7.8
70.3
7.8
0
0
0
75
200
75
200
75
200
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