
W528XXX
DESIGN GUIDE
3 -
FUNCTIONAL DESCRIPTION
1. Instruction Sets
The W528xxx family
PowerSpeech
program instruction sets include unconditional instructions and
conditional instructions. Most of these instructions are programmed by writing "LD (Load)" and "JP
(Jump)" commands and by modifying the content of the R0, EN, STOP, and MODE registers.
Registers
A. R0 Register
R0 is an 8-bit register that stores the entry values of from 0 to 255 voice groups. The structure of this
register is shown below:
R0:
Bit:
7
6
5
4
3
2
1
0
B. EN Register
EN is an 8-bit register that stores the rising/falling edge enable or disable status information for all
trigger pins, which determines whether each trigger pin is retriggerable, non-retriggerable, overwrite,
or non-overwrite. The 8-bit structure of this register and the rising or falling edge of the triggers
corresponding to each bit are shown below:
EN:
Bit:
7
6
5
4
3
2
1
0
Trigger:
4r
3r
2r
1r
4f
3f
2f
1f
The digits 1 to 4 represent triggers 1 to 4, respectively; "r" represents the rising edge; and "f"
represents the falling edge. When any one of the eight bits is set to "1," the rising or falling edge of
the corresponding trigger pin can be enabled, interrupting the current state.
C. STOP Register
The STOP register stores stop output status information to determine the voltage level of each stop
output pin. The 8-bit structure of this register and the stop output pin corresponding to each bit are
shown below:
STOP:
Bit:
7
6
5
4
3
2
1
0
STOP:
X
X
X
X
X
STPC
STPB
STPA
"X" indicates a "don't care" bit.
D. MODE Register
The MODE register is used to store operand information to select among various operating modes as
shown below.