
W561XXX DESIGN GUIDE
- 3 -
Edutainment toys.
FEATURE
Dual-channel operation via interrupt for automatic voice segment concatenation
Multi-engine processor, which is composed of
1)
μ
C, with basic ALU, 64-nibble RAM, and 8-bit timer.
2) Synth1, capable of voice syntheses with 4-bit ADPCM @SR=4.8/6/8/12 Khz and
8-bit PCM @SR=3/4/6 Khz.
3) Synth2, same as synth1.
4) PCM Melody (4-tone melody) and voice melody are possible with 16 Kbyte timbre
ROM.
5) The on-chip ROM is divided into two memory spaces: the main ROM is shared
among program execution, voice synthesis, and note storage; the timbre ROM is
used to store the PCM data of timbre.
Multi-tasking (+: in cascade, //: in parallel)
μ
C // (synth1 + PCM Melody) // synth2
Dynamic register control by LD instructions
Volume (VOL1/VOL2 for channel 1/2)
Melody: timbre0/1/2/3, tempo
PCM Melody (W561xxx only)
melody synthesis
Note number only limited by main ROM size
Note span: G1 - G5 (G3 as timbre, 49 notes, 4 octaves). G2 - G6, provided G4 as
timbre.
4 kind of envelope control in 16 steps
User-definable timbre library to achieve various kind of instrument effects
Midi-conversion utility provided
Selectable PCM Melody quality (SR=12 KHz, 1key/timbre)
Table size: 1/2/3/4/6/8/12/16 Kbyte per timbre.
Loop size: 128/256/512/1K/2K/4Kbit with respect to table size.
Low power consumption (@5 volt)
< 1 uA @standby
< 1 mA @operation, no load (Ring oscillator)
< 100 mA @operation with one SPK connected
Operating voltage: 2.4 - 5.5 volt
Truely interrupt, instead of polling
TG interrupt provided
Shared TG interrupt for P0/P1 inputs
Global TG interrupt enable (IEF.3) provided
Individual interrupt enable (PER0/PER1) provided
1 input port (P0), 2 I/O ports (P1 & P2), & 1 output port (P3)
8-level STACK shared by CALL, timer, synthesis, and TG.
SPK1/2 (or DAC1/2) provided for stereo outputs
Mixed channel outputs for SPK1 (or DAC1)
Programming style: downward compatible with
PowerSpeech
Single clock: 3 MHz ring or crystal selected by an external pin
W56000 ICE system for easy debugging