
W561XXX DESIGN GUIDE
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The first 128 RAM-mapped locations are 4-bit wide and are suitable for data exchanges. The last
128 addresses are used for those registers that got more than 4 bits.
RAM
64 x 4 bits RAM, R0..R63, can be used to store data. They can only be addressed directly. The
first eight locations, R0..R7, are used as
Working Register (WR),
denote as WR0 to WR7. They
are useful in data moves from other RAM-mapped locations. For convenience, users can denote
WR0 ~ WR7 as R0 ~ R7 to load data directly, and then rename to
WR0 ~ WR7 for moving the
data. The other data memories are used as general memory and can't operate directly with
another RAM.
Example :
(1) Load data
LD R10, 1001b ; the 4 bit value is loaded into the addressed location 10.
(2) Load & Move data
LD R2, 1001b ; Working Register location 2 (WR2) is named as R2 for loading
MV R63, WR2 ; data into it , and then renamed to WR2 to move data to R63.
Control Registers
ACC
The ACC (Accumulator) is generally modified during MOVE and ALU operations to reflect the
operation result. Branch instructions can be decided to be executed or not depending on the ACC
content.
MODE
3
2
1
Dynamic Control
Melody
Vol2
Vol1
Default vaules upon power up are "0000", indicating dynamic control is OFF for all three possible
parameters: melody timbre/tempo, channel1 volume, and channel2 volume; and clock source of
timer is 32 Hz.
MODE.0
Clock Source
0
32 Hz
1
32 KHz
The dynamic control feature of the W561xxx allows customers to change the parameters through
program control, in addition to fixed playback along with the voice segments or melody phrases.
Example :
LD MODE, 1101b ; Dynamic control of Melody and Volume 2 are ON
; clock source of Timer is 32 Khz
IER
3
2
Timer
TG
0: Disable (Default)
1: Enable
0
Timer clock
Overflow Period
30 mS - 8 S
30 uS - 8 mS
1
0
Reserved
Reserved