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參數資料
| 型號： | W561S40 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 音頻合成 |
| 英文描述： | 4-tone PCM Melody+ADPCM/PCM Voice Synthesizer(4音PCM音樂、ADPCM/PCM話音合成器) |
| 中文描述： | 40 SEC, SPEECH SYNTHESIZER |
| 文件頁數： | 16/62頁 |
| 文件大小： | 848K |
| 代理商： | W561S40 |
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W561XXX DESIGN GUIDE
- 16 -
The PSR register needs to be stored first after an interrupt happens along with general-purpose
ACC in order to prevent from possible changes made during ISR. They must be moved from
temporarily stored RAM locations to PSR and ACC for restoring initial values correctly.
Example :
SETB PSR.1 ; set the carry flag (CF) to 1
TF0 ( Trigger Flag of Port 0 )
TF0 is used to latch the individual trigger event of port 0 (pins P0.0 - P0.3). TF0 register is
organized as 4-bit binary register (TF0.0 to TF0.3). It can be read or cleared by "MV WRn , TF0",
and "CLR TF0" instructions. The bit descriptions are as follows:
3
2
P0.3
P0.2
Bit 0 = 1 Falling-edge detected on P0.0
Bit 1 = 1 Falling-edge detected on P0.1
Bit 2 = 1 Falling-edge detected on P0.2
Bit 3 = 1 Falling-edge detected on P0.3
Default value is 0000B upon power up. Since each bit of TF0 will be set up to 1 whenever a
falling-edge is detected on the corresponding pin ( no debounce time). The TF0 must be cleared
immediately after the ISR of dedicated TG interrupt is successfully invoked to prevent the
undesired disturbance which may be caused by glitch on port 0 ( see more detail in
Program
Example
section).
Example :
CLR TF0 ; clear the TF0 register
CLRB TF0.1 ; clear TF0 bit1
TF1 ( Trigger Flag of Port 1 )
3
2
P1.3
P1.2
Same as TF0 except for port P1, rather than port P0, when P1 is configured as trigger interrupt
input.
TIMER
7
6
5
4
This 8-bit timer downcounts every clock cycle, which is determined by the timer clock source.
Upon overflow conditions that occur when the timer changes from 00h to FFh, the W56000
generates the timer INT to allow manipulation of timed events. It starts to downcount after the
execution of "LD timer, operand". After the timer INT occurs under overflow conditions, the timer
stops downcounting. Users have to re-start the timer operation by loading the timer with an
appropriate value.
The timer interrupt happens every 30 uS - 8 second, depending on the selection of different
clock sources, and can be disabled by IER.
1
0
P0.1
P0.0
1
0
P1.1
P1.0
3
2
1
0
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| W561S50 | 4-tone PCM Melody+ADPCM/PCM Voice Synthesizer(4音PCM音樂、ADPCM/PCM話音合成器) |
| W561S60 | 4-tone PCM Melody+ADPCM/PCM Voice Synthesizer(4音PCM音樂、ADPCM/PCM話音合成器) |
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| W561S99 | 4-tone PCM Melody+ADPCM/PCM Voice Synthesizer(4音PCM音樂、ADPCM/PCM話音合成器) |
| W561XXX | 4-CH MELODY WITH VOICE SYNTHESIZER (BandDirectorTM Family) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W561S50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BandDirectorTM Family |
| W561S60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BandDirectorTM Family |
| W561S80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BandDirectorTM Family |
| W561S99 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BandDirectorTM Family |
| W561XXX | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4-CH MELODY WITH VOICE SYNTHESIZER (BandDirectorTM Family) |
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