
W561XXX DESIGN GUIDE
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The P0 port is interruptable trigger inputs with separate internal pull-up devices. This port is
usually regarded as TG1 - TG4 in previous PowerSpeech products. No internal debounce
circuits is available with P0, since the bounce is to be eliminated by means of user's program.
A common ISR, for P0 & P1 (provided that P1 is selected as input port), will be invoked once
a low-going edge is sensed on the port, the program is then used to further differentiate which
pin of the port is actually pressed down.
P1.0 - P1.3
These pins can be selected to be either inputs or outputs, depending on the status of IOR1
(I/O register 1). By setting the PCR1 (Pin Configuration Register 1), each selection can also
be defined as passive pull-up or floating for input pins, or defined as inverter or open drain
outputs. See Control Registers for further information. The P1 port is interruptable and
invokes the same ISR as P0, if selected as input.
P2.0 - P2.3
These pins can be selected to be either inputs or outputs, depending on the status of IOR2
(I/O register 2). By setting the PCR2 (Pin Configuration Register 2), each selection can also
be defined as passive pull-up or floating for input pins, or defined as inverter or open drain
outputs. See Control Registers for further information. The P2 port is a status port (not
interruptable, users have to move it to internal RAM for further processing), if selected as
input.
P3.0 - P3.3
The P3 is an
inverter type
output port.
VDD & VSS
VDD is the positive power supply, while VSS is the negative power supply. In order to prevent
possible power noises generated during motor driving from interfering the proper operations
of the internal POR circuit, which is essential to the POI(Power On Initialization) process of
the PowerSpeech synthesizers, two approaches are being adopted in the W561xxx one is to
use the /RESET pin, which is described in detail elsewhere, to fully reset the internal circuit
for a brand new start; the other is to place VDD and POR circuit apart as far as possible to
reduce the possibility of noise induction.
In order for the W561xxx to process the POI correctly, the VDD has to drop low enough and
rise quite quickly to initiate the internal POR circuit for generating the required pulse. Special
care goes to the discharge of VDD to nearly ground level to ensure proper operations.
TEST
The TEST pin is used solely for test purposes. It is internally pulled low by an NMOS device
with a 200K
resistance to prevent floating-gate conditions.