
W78C54
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Following tables show the interrupt informations and priority definitions.
Eight-source interrupt informations:
INTERRUPT
SOURCE
VECTOR
ADDRESS
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
0 (highest)
1
2
3
4
5
6
7 (lowest)
ENABLE
REQUIRED
SETTINGS
IE.0
IE.1
IE.2
IE.3
IE.4
IE.5
XICON.EX2
XICON.EX3
INTERRUPT
TYPE
EDGE/LEVEL
TCON.IT0
-
TCON.IT1
-
-
-
XICON.IT2
XICON.IT3
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
Timer/Counter 2
External Interrupt 2
External Interrupt 3
03H
0BH
13H
1BH
23H
2BH
33H
3BH
*Timer/Counter
***TL0, TH0, TL1, TH1, TL2, TH2, RCAP2L, RCAP2H
***TMOD - Timer 0, 1 mode (89H)
GATE
C//T
M1
M0
GATE
C//T
M1
M0
TIMR0
TIMR1
GATE:
Gating control. When set, Timer/counter x is enabled only while INTx pin is high and TRx
control pin is set. When cleared, Timer x is enabled whenever the TRx conrol bit is set.
Timer or Counter Selector. Cleared for timer operation. Set for counter operation.
M1 M0: Operating Mode
0 0: 13-bit Timer/Counter.
0 1: 16-bit Timer/Counter.
1 0: 8-bit auto-reload Timer/Counter. THx holds a value which is to be reloaded into TLx
each time it overflows.
1 1: Timer 0: TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only controlled by Timer 1 control bits.
Timer 1: Timer/counter 1 stopped.
C//T:
***TCON - Timer 0, 1 Control (88H)
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TF1: Timer 1 overflow flag. Set by hardware on timer/counter overflow. cleared by hardware when
processor vectors to interrupt routine.