
Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 66 -
Revision A2.0
I2C ADDRESS REGISTER
Bit:
7
I2ADDR.7 I2ADDR.6 I2ADDR.5
6
5
4
I2ADDR.4
3
I2ADDR.3
2
I2ADDR.2
1
I2ADDR.1 GC
0
Mnemonic: I2ADDR
Address: EAh
BIT
NAME
FUNCTION
7-1
I2ADDR
I2C Slave Address. The contents of the register are irrelevant when I2C is in
master mode. In the slave mode, the seven most significant bits must be loaded
with the MCU’s own slave address. The I2C hardware will react if the contents of
I2ADDR are matched with the received slave address.
0
GC
Enable General Call Function. The GC bit is set the I2C port hardware will respond
to General Call address (00H). Clear GC bit to disable general call function.
NVM HIGH BYTE ADDRESS
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
-
NVMADDR
H.10
NVMADDR
H.9
NVMADDR
H.8
Mnemonic:
NVMADDRH
Address:
EB
h
BIT
NAME
FUNCTION
7-3
-
NVMADDRH.10 ~
NVMADDRH.8
Reserved.
2-0
NVM High byte address
I2C DATA REGISTER
Bit:
7
I2DAT.7
6
I2DAT.6
5
I2DAT.5
4
I2DAT.4
3
I2DAT.3
2
I2DAT.2
1
I2DAT.1
0
I2DAT.0
Mnemonic: I2DAT
I2DAT.7-0
Address: ECh
The data register of I2C channel.
I2C STATUS REGISTER
Bit:
7
B7
6
B6
5
B5
4
B4
3
B3
2
0
1
0
0
0
Mnemonic: I2STATUS
Address: EDh
BIT
NAME
FUNCTION
7-0
I2STATUS
The Status Register of I2C. The three least significant bits are always 0. The five
most significant bits contain the status code. There are 23 possible status
codes. When I2STATUS contains F8H, no serial interrupt is requested. All other
I2STATUS values correspond to defined I2C states. When each of these states
is entered, the I2C1 interrupt is requested (SI = 1). A valid status code is present
in I2STATUS one machine cycle after SI is set by hardware and is still present
one machine cycle after SI has been reset by software. In addition, states 00H
stands for a Bus Error. A Bus Error occurs when a START or STOP condition is
present at an illegal position in the formation frame. Example of illegal position
are during the serial transfer of an address byte, a data byte or an acknowledge
bit.