
Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 64 -
Revision A2.0
BIT
NAME
FUNCTION
7
PWMEOM
PWM Channel 0, 2 and 4 Output Mode.
0 = Disable PWM channels 0, 2 and 4 to pwm output pins.
1 = Enable PWM channels 0, 2 and 4 to pwm output pins.
6
PWMOOM
PWM Channel 1, 3 and 5 Output Mode.
0 = Disable PWM channels 1, 3 and 5 to pwm output pins.
1 = Enable PWM channels 1, 3 and 5 to pwm output pins.
5
PWM6OM
PWM Channel 6 Output Mode.
0 = Disable PWM channel 6 to pwm output pin.
1 = Enable PWM channel 6 to pwm output pin.
4
PWM7OM
PWM Channel 7 Output Mode.
0 = Disable PWM channel 7 to pwm output pin.
1 = Enable PWM channel 7 to pwm output pin.
3-1
-
Reserved.
0
BKF
The External Brake Pin Flag.
0 = The PWM is not brake.
1 = The PWM is brake by external brake pin. It will be cleared by software.
Together with option bits (PWMEE and PWMOE), PWMEOM, PWMOOM, PWM6OM and PWM7OM
control the PWM pin structure, as follow;
PWMEE/PWMOE
(OPTION BITS)
PWMEOM/PWMOOM
/PWM6OM/PWM7OM
PIO.X
(X = 0-7)
PIN STRUCTURES
X
0
X
Tri-state
Quasi (I/O output)
Push Pull (PWM output)
Push Pull (I/O output)
1 (D
isable
)
0 (Enable)
0 (Enable)
1
1
1
X
0
1
Table 7-2: PWM pin structures (during internal rom execution)
PWMEE/PWMOE
(OPTION BITS)
PWMEOM/PWMOOM
/PWM6OM/PWM7OM
PIO.X
(X = 0-7)
PIN
OUTPUT
PIN STRUCTURES
1 (Disable)
X
X
External
access
External
access
Push Pull
0 (Enable)
X
X
Push Pull (strong)
Table 7-3: PWM pin structures (during external rom execution)
Note: PWMEOM/PWMOOM/PWM6OM/PWM7OM are cleared to zero when CPU in reset state.
Thus, the port pins that multi-function with PWM will be tristated on default. User is required to set
the bits to 1 to enable GPIO/PWM outputs.