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參數(shù)資料
| 型號： | W83194R-67A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | XO, clock |
| 英文描述： | 100MHZ 3-DIMM CLOCK FOR VIA MVP4 |
| 中文描述： | 124 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大小： | 237K |
| 代理商： | W83194R-67A |
W83194R-67A
PRELIMINARY
Publication Release Date: Feb. 1999
- 15 - Revision 0.30
10.0 POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
CPU_STOP#
CPUCLK[0:3]
SDRAM
3
4
1
2
3
4
1
2
For synchronous Chipset, CPU_STOP# pin is an asynchronous
active low
input pin used to stop
the CPU clocks for low power operation. This pin is asserted synchronously by the external control
logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run
while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume
output with full pulse width. In this case, CPU
c
locks on latency
is less than 4 CPU clocks and
c
locks off latency
is less then 4 CPU clocks.
10.2 PCI_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
PCI_STOP#
PCICLK[0:5]
1
2
1
2
For synchronous Chipset, PCI_STOP# pin is an asynchronous
a
ctive low
input pin used to stop
the PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control
logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run
while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume
output with full pulse width. In this case, PCI
c
locks on latency
is less than 2 PCI clocks and
c
locks off latency
is less then 2 PCI clocks.
相關PDF資料 |
PDF描述 |
|---|---|
| W83194R-67B | 100MHZ 3-DIMM Clock For Via MVP4(用于主流通路芯片組的頻率為100MHZ的三雙列直插存儲模塊式時鐘) |
| W83194R | 166MHZ CLOCK FOR SIS CHIPSET |
| W83194R-630A | 166MHZ CLOCK FOR SIS CHIPSET |
| W83195AR-25 | 200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET |
| W83195BR-S | STEPLESS 200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W83194R-67A/-67B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:133MHz(Adding 97MHz) VIA MVP4 Clock Gen.. 3-DIMM. with S.S.T. |
| W83194R-67B | 制造商:WINBOND 制造商全稱:Winbond 功能描述:100MHZ 3-DIMM CLOCK FOR VIA MVP4 |
| W83194R-81 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:100MHZ CLOCK FOR SIS CHIPSET |
| W83194R-KX | 制造商:WINBOND 制造商全稱:Winbond 功能描述:133MHZ 3-DIMM K7 CLOCK |
| W83194R-WE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|48PIN|PLASTIC |
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