
W83697HF/F
Publication Release Date: Feb. 2002
- 47 - Revision 0.70
TABLE 4-1 UART Register Bit Map
Bit Number
1
2
RX Data
Bit 1
Register Address Base
+ 0
BDLAB = 0
0
3
4
5
6
7
Receiver
Buffer
Register
(Read Only)
Transmitter
Buffer Register
(Write Only)
Interrupt Control
Register
RBR
RX Data
Bit 0
RX Data
Bit 2
RX Data
Bit 3
RX Data
Bit 4
RX Data
Bit 5
RX Data
Bit 6
RX Data
Bit 7
+ 0
BDLAB = 0
TBR
TX Data
Bit 0
TX Data
Bit 1
TX Data
Bit 2
TX Data
Bit 3
TX Data
Bit 4
TX Data
Bit 5
TX Data
Bit 6
TX Data
Bit 7
+ 1
BDLAB = 0
ICR
RBR Data
Ready
Interrupt
Enable
(ERDRI)
"0" if
Interrupt
Pending
TBR
Empty
Interrupt
Enable
(ETBREI)
Interrupt
Status
Bit (0)
RCVR
FIFO
Reset
USR
Interrupt
Enable
(EUSRI)
HSR
Interrupt
Enable
(EHSRI)
0
0
0
0
+ 2
Interrupt Status
Register
(Read Only)
ISR
Interrupt
Status
Bit (1)
XMIT
FIFO
Reset
Interrupt
Status
Bit (2)**
DMA
Mode
Select
0
0
FIFOs
Enabled
**
RX
Interrupt
Active Level
(LSB)
Set
Silence
Enable
(SSE)
FIFOs
Enabled
**
RX
Interrupt
Active Level
(MSB)
Baudrate
Divisor
Latch
Access Bit
(BDLAB)
0
+ 2
UART FIFO
Control
Register
(Write Only)
UART Control
Register
UFR
FIFO
Enable
Reserved
Reversed
+ 3
UCR
Data
Length
Select
Bit 0
(DLS0)
Data
Terminal
Ready
(DTR)
RBR Data
Ready
(RDR)
Data
Length
Select
Bit 1
(DLS1)
Request
to
Send
(RTS)
Overrun
Error
(OER)
Multiple
Stop Bits
Enable
(MSBE)
Parity
Bit
Enable
(PBE)
Even
Parity
Enable
(EPE)
Parity
Bit Fixed
Enable
PBFE)
+ 4
Handshake
Control
Register
HCR
Loopback
RI
Input
IRQ
Enable
Internal
Loopback
Enable
0
0
+ 5
UART Status
Register
USR
Parity Bit
Error
(PBER)
No Stop
Bit
Error
(NSER)
DCD
Toggling
(TDCD)
Bit 3
Silent
Byte
Detected
(SBD)
Clear
to Send
(CTS)
Bit 4
TBR
Empty
(TBRE)
TSR
Empty
(TSRE)
RX FIFO
Error
Indication
(RFEI) **
Data Carrier
Detect
(DCD)
Bit 7
+ 6
Handshake
Status Register
HSR
CTS
Toggling
(TCTS)
Bit 0
DSR
Toggling
(TDSR)
Bit 1
RI Falling
Edge
(FERI)
Bit 2
Data Set
Ready
(DSR)
Bit 5
Ring
Indicator
(RI)
Bit 6
+ 7
User Defined
Register
Baudrate
Divisor Latch
Low
Baudrate
Divisor Latch
High
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
UDR
+ 0
BDLAB = 1
BLL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
+ 1
BDLAB = 1
BHL
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15