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參數資料
| 型號： | W89C926 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER |
| 中文描述： | PCMCIA以太網雙絞線網絡接口控制器 |
| 文件頁數： | 5/48頁 |
| 文件大小： | 395K |
| 代理商： | W89C926 |
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W89C926 PENTIC+
Publication Release Date: January 1996
- 5 -
Revision A1
Pin Description, continued
NAME
NUMBER
TYPE
DESCRIPTION
Memory Support Interface
MSA0-7
MSA8-10
MSA11-13
MSA14-16
90-97
82, 81, 78
80, 98, 84
99, 69, 70
O/TTL
Memory Support Address:
Latched address used to decode accesses to the on-
board memory.
MSD0-2
MSD3-7
89-87
71-75
IO/3SH
I/O/3SH
Memory Support Data Bus:
Bidirectional on-board memory data bus.
EEPROM Interface:
During the EEPROM auto-load or read/write sequence,
MSD0 is used as a serial data input/output from/to
EEPROM, MSD1 outputs EEPROM commands to
EEPROM, and MSD2 sends a clock with a period of 1.2
microseconds. This function is available only when
EECS/FCS is low during H/W reset.
RCS
77
O/TTL
SRAM Chip Select:
RCS
is asserted by the PENTIC+ for SRAM chip
enable during buffer memory access.
EECS/
FCS
76
O/3SH
I/3SH
Nonvolatile Memory Chip Select:
EECS/FCS is asserted by the PENTIC+ for chip enable
during nonvolatile memory access. It is active low for
flash memory enable and active high for EEPROM chip
enable.
Nonvolatile Memory Detection:
During H/W reset, the PENTIC+ will determine the
existing nonvolatile memory type by sampling the
voltage level on this pin. If this pin is externally pulled
high with a 470K ohm resistor, the PENTIC+ will
determine that the memory is a flash memory; if the pin
is pulled low with a 470K ohm resistor, it will determine
that the memory is an EEPROM.
MSRD
79
O/TTL
Memory Support Read:
MSRD
is asserted by the PENTIC+ to strobe read data
from the on-board memory. Both SRAM and flash
memory use
MSRD
as the read command strobe.
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